Y8( 'tsd,px30-ringneck-haikourockchip,px30 +07Theobroma Systems PX30-uQ7 SoM on Haikou devkitaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff390000/mmc@ff380000/i2c@ff190000/rtc@6f/i2c@ff180000/pmic@20/ethernet@ff360000/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZ  +cpu@1cpuarm,cortex-a35psciZ  +cpu@2cpuarm,cortex-a35psciZ  + cpu@3cpuarm,cortex-a35psciZ  + idle-states3pscicpu-sleeparm,idle-state@Qhxy+cluster-sleeparm,idle-state@Qhy+opp-table-0operating-points-v2+opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkin%psci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal2HVh tripstrip-point-0xppassivetrip-point-1xLpassive+soc-critx8 criticalcooling-mapsmap0 gpu-thermal2dHh tripsgpu-thresholdxppassivegpu-targetxLpassive+gpu-critx8 criticalcooling-mapsmap0 xin24m fixed-clock%n6xin24m+gpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller++ipower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd++io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB  RBRB$RBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&2baudclkapb_pclk>''CtxrxMWddefault r()*okayi2s@ff060000rockchip,px30-i2s-tdm  2mclk_txmclk_rxhclk>''Ctxrx|+ tx-mrx-mddefaultr,-./okay+i2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  2i2s_clki2s_hclk>''Ctxrxddefaultr0123 disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s 2i2s_clki2s_hclk>''Ctxrxddefaultr4567 disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   +syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+++io-domains rockchip,px30-io-voltage-domainokay%8 %%&%49B%lvdsrockchip,px30-lvdsV:[dphy|+elvds disabledports+port@0+endpoint@0u;+endpoint@1u<+port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I2baudclkapb_pclk>''CtxrxMWddefault r=>? disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J2baudclkapb_pclk>''CtxrxMWddefaultr@ disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K2baudclkapb_pclk>''CtxrxMWddefault rABC disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L2baudclkapb_pclk>'' CtxrxMWddefault rDEF disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M2baudclkapb_pclk>' ' CtxrxMWddefaultrGokay H i2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN 2i2cpclk ddefaultrI+okaypmic@20rockchip,rk809  HrJddefault%xin32kKKKK%%%KregulatorsDCDC_REG1vdd_log-~Ep]qrregulator-state-mem~DCDC_REG2vdd_arm-~Ep]qr+regulator-state-mem~DCDC_REG3vcc_ddrrregulator-state-memDCDC_REG4 vcc_3v0_1v8-w@E-r+9regulator-state-mem-DCDC_REG5vcc_3v3-2ZE2Zr+%regulator-state-mem2ZLDO_REG2vcc_1v8-w@Ew@r+fregulator-state-memw@LDO_REG3vcc_1v0-B@EB@rregulator-state-memB@LDO_REG5 vccio_sd-w@E2Zr+8regulator-state-mem2ZLDO_REG7r-B@EB@vcc_lcdregulator-state-memB@LDO_REG8 vcc_1v8_lcd-w@Ew@rregulator-state-memw@LDO_REG9 vcca_1v8-w@Ew@rregulator-state-memw@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO 2i2cpclk ddefaultrL+okayfan@18 ti,amc6821rtc@6f isil,isl1208oi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP 2i2cpclk  ddefaultrM+okaycodec@a fsl,sgtl5000 NOPQ+i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q 2i2cpclk  ddefaultrR+okayeeprom@50P atmel,24c01 Pspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U2spiclkapb_pclk>' ' CtxrxddefaultrSTUV+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V2spiclkapb_pclk>''CtxrxddefaultrWXYZ[+okaywatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S 2pwmpclkddefaultr\%okaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S 2pwmpclkddefaultr]% disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S 2pwmpclkddefaultr^% disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S 2pwmpclkddefaultr_% disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T 2pwmpclkddefaultr`% disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T 2pwmpclkddefaultra% disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T 2pwmpclkddefaultrb% disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T 2pwmpclkddefaultrc% disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& 2pclktimerdma-controller@ff240000arm,pl330arm,primecell$@0 2apb_pclkG+'tsadc@ff280000rockchip,px30-tsadc( $R,bP,X2tsadcapb_pclk tsadc-apb|+wdinitdefaultsleeprdedokay+ saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-W2saradcapb_pclk saradc-apbokayfnvmem@ff290000rockchip,px30-otp)@/Za2otpapb_pclkphyphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ g& 2xin24mgpll|+%8R@IbFq рр +clock-controller@ff2bc000rockchip,px30-pmucru+g2xin24m|+%R&&& bG+&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & 2phyclk%Rh usb480m_phyokay+hhost-port D  linestateokay+kotg-port$BA@ otg-bvalidotg-idlinestateokay+jphy@ff2e0000rockchip,px30-dsi-dphy.& E 2refpclk>apbi  disabled+:phy@ff2f0000rockchip,px30-csi-dphy/@F2pclki /apb|+ disabled+usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >2otg(otg0BQ@ Vj [usb2-phyiokayusb@ff340000 generic-ehci4 <Vk[usbiokayusb@ff350000 generic-ohci5 =Vk[usbiokayethernet@ff360000rockchip,px30-gmac6 + macirq@>??@ACL[2stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed|+`rmiiddefaultrlmi ^ stmmacethokay iny PP%outputmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD2biuciuciu-driveciu-sampleрddefaultropqriokay8% 6H?JPmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF2biuciuciu-driveciu-sampleрddefault rstui  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH2biuciuciu-driveciu-sampleрddefault rvwxi okayVesy~J%9spi@ff3a0000 rockchip,sfc:@ 8:2clk_sfchclk_sfc rz{|ddefaulti  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 972ahbnfcR7bрddefault r}~i  disabledopp-table-1operating-points-v2+opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.-  jobmmugpuIi okay+video-codec@ff442000rockchip,px30-vpuD PO  vepuvdpu 2aclkhclki iommu@ff442800rockchip,iommuD( Q 2aclkifacei +dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD2pclkV:[dphyi =apb|++ disabledports+port@0+endpoint@0u+endpoint@1u+port@1vop@ff460000rockchip,px30-vop-bigF M2aclk_vopdclk_vophclk_vop345 axiahbdclki  disabledport++ endpoint@0u+endpoint@1u+;iommu@ff460f00rockchip,iommuF M 2aclkifacei  disabled+vop@ff470000rockchip,px30-vop-litG N2aclk_vopdclk_vophclk_vop789 axiahbdclki  disabledport++ endpoint@0u+endpoint@1u+<iommu@ff470f00rockchip,iommuG N 2aclkifacei  disabled+isp@ff4a0000rockchip,px30-cif-ispJ$FIJ  ispmimipi 3_2ispaclkhclkpclkV[dphyi  disabledports+port@0+iommu@ff4a8000rockchip,iommuJ F 2aclkifacei +qos@ff518000rockchip,px30-qossysconQ +qos@ff520000rockchip,px30-qossysconR +$qos@ff52c000rockchip,px30-qossysconR +qos@ff538000rockchip,px30-qossysconS +qos@ff538080rockchip,px30-qossysconS +qos@ff538100rockchip,px30-qossysconS +qos@ff538180rockchip,px30-qossysconS +qos@ff540000rockchip,px30-qossysconT +qos@ff540080rockchip,px30-qossysconT +qos@ff548000rockchip,px30-qossysconT +qos@ff548080rockchip,px30-qossysconT + qos@ff548100rockchip,px30-qossysconT +!qos@ff548180rockchip,px30-qossysconT +"qos@ff548200rockchip,px30-qossysconT +#qos@ff550000rockchip,px30-qossysconU +qos@ff550080rockchip,px30-qossysconU +qos@ff550100rockchip,px30-qossysconU +qos@ff550180rockchip,px30-qossysconU +qos@ff558000rockchip,px30-qossysconU +qos@ff558080rockchip,px30-qossysconU +pinctrlrockchip,px30-pinctrl|++gpio@ff040000rockchip,gpio-bank &+Hgpio@ff250000rockchip,gpio-bank% \+gpio@ff260000rockchip,gpio-bank& ]bios-disable-override-hog bios_disable_override bios-disable-n-hog bios_disable  gpio@ff270000rockchip,gpio-bank' ^+npcfg-pull-up +pcfg-pull-down pcfg-pull-none ,+pcfg-pull-none-2ma , 9pcfg-pull-up-2ma  9pcfg-pull-up-4ma  9+pcfg-pull-none-4ma , 9pcfg-pull-down-4ma  9pcfg-pull-none-8ma , 9+pcfg-pull-up-8ma  9+pcfg-pull-none-12ma , 9 +pcfg-pull-up-12ma  9 +pcfg-pull-none-smt , H+pcfg-output-highpcfg-output-low ]pcfg-input-high  h+pcfg-input hi2c0i2c0-xfer u +Ii2c1i2c1-xfer u+Li2c2i2c2-xfer u+Mi2c3i2c3-xfer u  +Rtsadctsadc-otp-pin u+dtsadc-otp-out u+euart0uart0-xfer u  +(uart0-cts u +)uart0-rts u +*uart1uart1-xfer u+=uart1-cts u+>uart1-rts u+?uart2-m0uart2m0-xfer u+@uart2-m1uart2m1-xfer u uart3-m0uart3m0-xfer uuart3m0-cts uuart3m0-rts uuart3-m1uart3m1-xfer u+Auart3m1-cts u +Buart3m1-rts u +Cuart4uart4-xfer u+Duart4-cts u+Euart4-rts u+Fuart5uart5-xfer u+Guart5-cts uuart5-rts uspi0spi0-clk u+Sspi0-csn u+Tspi0-miso u +Uspi0-mosi u +Vspi0-clk-hs uspi0-miso-hs u spi0-mosi-hs u spi1spi1-clk u+Wspi1-csn0 u +Xspi1-csn1 u +Yspi1-miso u+Zspi1-mosi u +[spi1-clk-hs uspi1-miso-hs uspi1-mosi-hs u pdmpdm-clk0m0 updm-clk0m1 updm-clk1 updm-sdi0m0 updm-sdi0m1 updm-sdi1 updm-sdi2 updm-sdi3 updm-clk0m0-sleep updm-clk0m1-sleep updm-clk1-sleep updm-sdi0m0-sleep updm-sdi0m1-sleep updm-sdi1-sleep updm-sdi2-sleep updm-sdi3-sleep ui2s0i2s0-8ch-mclk ui2s0-8ch-sclktx u+,i2s0-8ch-sclkrx u i2s0-8ch-lrcktx u+-i2s0-8ch-lrckrx u i2s0-8ch-sdo0 u+.i2s0-8ch-sdo1 ui2s0-8ch-sdo2 ui2s0-8ch-sdo3 ui2s0-8ch-sdi0 u+/i2s0-8ch-sdi1 u i2s0-8ch-sdi2 u i2s0-8ch-sdi3 ui2s1i2s1-2ch-mclk ui2s1-2ch-sclk u+0i2s1-2ch-lrck u+1i2s1-2ch-sdi u+2i2s1-2ch-sdo u+3i2s2i2s2-2ch-mclk ui2s2-2ch-sclk u+4i2s2-2ch-lrck u+5i2s2-2ch-sdi u+6i2s2-2ch-sdo u+7sdmmcsdmmc-clk u+osdmmc-cmd u+psdmmc-det u+qsdmmc-bus1 usdmmc-bus4@ u+rsdiosdio-clk u+usdio-cmd u+tsdio-bus4@ u+semmcemmc-clk u +vemmc-cmd u +wemmc-rstnout u emmc-bus1 uemmc-bus4@ uemmc-bus8 u+xemmc-reset u +flashflash-cs0 u+flash-rdy u +flash-dqs u +flash-ale u +}flash-cle u +flash-wrn u +flash-csl uflash-rdn u+flash-bus8 u+~sfcsfc-bus4@ u+|sfc-bus2 usfc-cs0 u+{sfc-clk u +zlcdclcdc-rgb-dclk-pin ulcdc-rgb-m0-hsync-pin ulcdc-rgb-m0-vsync-pin ulcdc-rgb-m0-den-pin ulcdc-rgb888-m0-data-pins u     lcdc-rgb666-m0-data-pins u     lcdc-rgb565-m0-data-pins u     lcdc-rgb888-m1-data-pins u   lcdc-rgb666-m1-data-pins u   lcdc-rgb565-m1-data-pins u   pwm0pwm0-pin u+\pwm1pwm1-pin u+]pwm2pwm2-pin u +^pwm3pwm3-pin u+_pwm4pwm4-pin u+`pwm5pwm5-pin u+apwm6pwm6-pin u+bpwm7pwm7-pin u+cgmacrmii-pins u +lmac-refclk-12ma u +mmac-refclk u cif-m0cif-clkout-m0 u dvp-d2d9-m0 u   dvp-d0d1-m0 u d10-d11-m0 ucif-m1cif-clkout-m1 udvp-d2d9-m1 u  dvp-d0d1-m1 ud10-d11-m1 uispisp-prelight uledsmodule-led-pin u+sd-card-led-pin u +pmicpmic-int u+Jhaikouhaikou-keys-pinP u+emmc-pwrseqmmc-pwrseq-emmcrddefault +yleds gpio-ledsddefaultrokayled-0  heartbeat heartbeat led-1 n  mmc2 sd vccsys-regulatorregulator-fixed vcc5v0_sysr-LK@ELK@+Kchosen serial0:115200n8gpio-keys gpio-keysrddefaultbutton-batlow-n BATLOW#  nbutton-slp-btn-n SLP_BTN#  button-wake-n WAKE#  switch-lid-btn-n LID_BTN#   ni2s0-soundsimple-audio-card i2s Haikou,I2S-codec  , Ksimple-audio-card,codec m w+simple-audio-card,cpu msgtl5000-oscillator fixed-clock%w+Ndc-12v-regulatorregulator-fixeddc_12vr-E+vcc3v3-baseboard-regulatorregulator-fixedvcc3v3_baseboardr-2ZE2Z +Pvcc5v0-baseboard-regulatorregulator-fixedvcc5v0_baseboardr-LK@ELK@ +vdda-codec-regulatorregulator-fixed vdda_codec-2ZE2Z +Ovddd-codec-regulatorregulator-fixed vddd_codec-jEj +Q compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0mmc1rtc0rtc1ethernet0mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cellsrockchip,trcm-sync-tx-only#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio-oscgpi-supplyphysphy-namesrockchip,outputremote-endpointrts-gpiosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendVDDA-supplyVDDIO-supplyVDDD-supplypagesizevcc-supplynum-cs#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usphy-supplyclock_in_outbus-widthfifo-depthmax-frequencyvqmmc-supplysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50cap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpvmmc-supplymmc-hs200-1_8vsupports-emmcmmc-pwrseqnon-removableiommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsoutput-highline-namegpio-hoginputbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-lowinput-enablerockchip,pinsreset-gpiosfunctionlinux,default-triggercolorstdout-pathlabellinux,codelinux,input-typesimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssimple-audio-card,frame-mastersimple-audio-card,bitclock-mastersound-daisystem-clock-fixedvin-supply