Z8(( 2$xunlong,orangepi-5rockchip,rk3588s +7Xunlong Orange Pi 5aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1c0000/mmc@fe2c0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55psci"5 < L0,a q~@@  cpu@100cpuarm,cortex-a55psci"5 a q~@@ cpu@200cpuarm,cortex-a55psci"5 a q~@@ cpu@300cpuarm,cortex-a55psci"5 a q~@@ cpu@400cpuarm,cortex-a76psci"5 < L0,a q~@@cpu@500cpuarm,cortex-a76psci"5 a q~@@cpu@600cpuarm,cortex-a76psci"5 < L0,a q~@@cpu@700cpuarm,cortex-a76psci"5 a q~@@ idle-statespscicpu-sleeparm,idle-state#4Kd\xl l2-cache-l0caches@} l2-cache-l1caches@}l2-cache-l2caches@}l2-cache-l3caches@}l2-cache-b0caches@}l2-cache-b1caches@}l2-cache-b2caches@}l2-cache-b3caches@}l3-cachecaches0@}display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemgpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf < L 5 corecoregroupstacks 0\]^ jobmmugpu- ;okayBopp-tableoperating-points-v2opp-300000000N U L L Popp-400000000Nׄ U L L Popp-500000000Ne U L L Popp-600000000N#F U L L Popp-700000000N)' U ` ` Popp-800000000N/ U q q Popp-900000000N5 U 5 5 Popp-1000000000N; U P P Pusb@fc000000rockchip,rk3588-dwc3snps,dwc3@5 ref_clksuspend_clkbus_clkcotg k !pusb2-phyusb3-phy zutmi_wide-R;okay6portendpointF"usb@fc800000"rockchip,rk3588-ehcigeneric-ehci5#k$pusb-;okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci5#k$pusb-;okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci5%k&pusb-;okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci5%k&pusb-;okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(5jihkr& ref_clksuspend_clkbus_clkutmipipechostk' pusb3-phy zutmi_wide4V;okayiommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-syncp ;disablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-syncp ;disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXfsyscon@fd58c000rockchip,rk3588-sys-grfsysconXasyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ bsyscon@fd5a6000rockchip,rk3588-vo-grfsysconZ` 5syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ5csyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@syscon@fd5b0000rockchip,rk3588-php-grfsyscon[(syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@0rockchip,rk3588-usb2phy5 phyclk usb480m_phy0m}phyapb;okayotg-port;okay syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy5 phyclk usb480m_phy2o}phyapb;okay#host-port;okay$syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy5 phyclk usb480m_phy3p }phyapb;okay%host-port;okay&syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|<]q@LA.2Fq)׫ׄe/ׄ eZ р (i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=5ts  i2cpclk)default+;okayregulator@42rockchip,rk8602Bvdd_cpu_big0_s0 dp#;P*regulator-state-mem[regulator@43 rockchip,rk8603rockchip,rk8602Cvdd_cpu_big1_s0 dp#;P*regulator-state-mem[serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK5 baudclkapb_pclkt++ytxrx,default ;disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5  pwmpclk-default ;disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5  pwmpclk.default ;disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5  pwmpclk/default ;disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05  pwmpclk0default ;disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfddpower-controller!rockchip,rk3588-power-controller+;okaypower-domain@8+power-domain@9  5!#" 123+power-domain@10 5!#"4power-domain@11 5!#"5power-domain@12 56789power-domain@13 +power-domain@14(5:power-domain@15 5;power-domain@165 <=>+power-domain@17 5 ?@Apower-domain@215 BCDEFGHI+power-domain@235CAJpower-domain@14 5:power-domain@155;power-domain@225Kpower-domain@245[Z]LM+power-domain@2585ZNpower-domain@2685QOPpower-domain@2705QRST+power-domain@28 5UVpower-domain@29(5WXpower-domain@305z{Ypower-domain@31@5WZ[\]power-domain@33!5WZ[power-domain@34"5WZ[power-domain@37%52^power-domain@38&545power-domain@40(_video-codec@fdc70000rockchip,rk3588-av1-vpulvdpu<ACLׄׄ5AC  aclkhclk- vop@fdd90000rockchip,rk3588-vop BPvopgamma-lut85]\abcd[7 aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop`-abcd ;disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~5]\  aclkifacep- ;disabled`i2s@fddc0000rockchip,rk3588-i2s-tdm5 mclk_txmclk_rxhclk<teytx-}tx-m ;disabledi2s@fddf0000rockchip,rk3588-i2s-tdm5445 mclk_txmclk_rxhclk<1teytx-}tx-m ;disabledi2s@fddfc000rockchip,rk3588-i2s-tdm500, mclk_txmclk_rxhclk<-teyrx-}rx-m ;disabledqos@fdf35000rockchip,rk3588-qossysconP 6qos@fdf35200rockchip,rk3588-qossysconR 7qos@fdf35400rockchip,rk3588-qossysconT 8qos@fdf35600rockchip,rk3588-qossysconV 9qos@fdf36000rockchip,rk3588-qossyscon` Yqos@fdf39000rockchip,rk3588-qossyscon ^qos@fdf3d800rockchip,rk3588-qossyscon _qos@fdf3e000rockchip,rk3588-qossyscon [qos@fdf3e200rockchip,rk3588-qossyscon Zqos@fdf3e400rockchip,rk3588-qossyscon \qos@fdf3e600rockchip,rk3588-qossyscon ]qos@fdf40000rockchip,rk3588-qossyscon Wqos@fdf40200rockchip,rk3588-qossyscon Xqos@fdf40400rockchip,rk3588-qossyscon Qqos@fdf40500rockchip,rk3588-qossyscon Rqos@fdf40600rockchip,rk3588-qossyscon Sqos@fdf40800rockchip,rk3588-qossyscon Tqos@fdf41000rockchip,rk3588-qossyscon Uqos@fdf41100rockchip,rk3588-qossyscon Vqos@fdf60000rockchip,rk3588-qossyscon <qos@fdf60200rockchip,rk3588-qossyscon =qos@fdf60400rockchip,rk3588-qossyscon >qos@fdf61000rockchip,rk3588-qossyscon ?qos@fdf61200rockchip,rk3588-qossyscon @qos@fdf61400rockchip,rk3588-qossyscon Aqos@fdf62000rockchip,rk3588-qossyscon :qos@fdf63000rockchip,rk3588-qossyscon0 ;qos@fdf64000rockchip,rk3588-qossyscon@ Jqos@fdf66000rockchip,rk3588-qossyscon` Bqos@fdf66200rockchip,rk3588-qossysconb Cqos@fdf66400rockchip,rk3588-qossyscond Dqos@fdf66600rockchip,rk3588-qossysconf Eqos@fdf66800rockchip,rk3588-qossysconh Fqos@fdf66a00rockchip,rk3588-qossysconj Gqos@fdf66c00rockchip,rk3588-qossysconl Hqos@fdf66e00rockchip,rk3588-qossysconn Iqos@fdf67000rockchip,rk3588-qossysconp Kqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 4qos@fdf71000rockchip,rk3588-qossyscon 5qos@fdf72000rockchip,rk3588-qossyscon 1qos@fdf72200rockchip,rk3588-qossyscon" 2qos@fdf72400rockchip,rk3588-qossyscon$ 3qos@fdf80000rockchip,rk3588-qossyscon Nqos@fdf81000rockchip,rk3588-qossyscon Oqos@fdf81200rockchip,rk3588-qossyscon Pqos@fdf82000rockchip,rk3588-qossyscon Lqos@fdf82200rockchip,rk3588-qossyscon" Mdfi@fe060000rockchip,rk3588-dfi@&0:fpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie(0?05CH>MR) aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr2C`Vggggdu0h0k' ppcie-phy-"T @ @0 @@dbiapbconfig). }pwrpipe+ ;disabledlegacy-interrupt-controller2 gpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie(@O05DI?NSs) aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr2C`Viiiidu@h@kj ppcie-phy-"T @ @0 A@dbiapbconfig*/ }pwrpipe+;okay kllegacy-interrupt-controller2 iethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(567Y^50 stmmacethclk_mac_refpclk_macaclk_macptp_ref-!$ }stmmacetha(mn o;okay(output5p @rgmii-rxidqrstudefaultIBmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22RN b k pstmmac-axi-configt~mrx-queues-confignqueue0queue1tx-queues-configoqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(5b_eTo satapmaliverxoobrefasic+ ;disabledsata-port@0@kj psata-phy  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(5dagVq satapmaliverxoobrefasic+ ;disabledsata-port@0@k' psata-phy  spi@fe2b0000 rockchip,sfc+@5/0 clk_sfchclk_sfc+;okaydefaultvflash@0jedec,spi-nor*mmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ 5   biuciuciu-driveciu-sample; рdefaultwxyz-(;okay FWbiq{|mmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ 5 biuciuciu-driveciu-sample; default}-% ;disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.<-., L n6 (5,*+-. corebusaxiblocktimer ~default(}corebusaxiblocktimer ;disabledi2s@fe470000rockchip,rk3588-i2s-tdmG5+/( mclk_txmclk_rxhclk<)-t++ytxrx-&*+ }tx-mrx-mdefault( ;disabledi2s@fe480000rockchip,rk3588-i2s-tdmH5y}u mclk_txmclk_rxhclkt++ytxrx^_ }tx-mrx-mdefault( ;disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI5 i2s_clki2s_hclk<tytxrx-&default ;disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ5% i2s_clki2s_hclk<"tytxrx-&default ;disabledinterrupt-controller@fe600000 arm,gic-v3 `h a82+msi-controller@fe640000arm,gic-v3-itsdhmsi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW5n  apb_pclk +dma-controller@fea30000arm,pl330arm,primecell@ XY5o  apb_pclk i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c5{  i2cpclk>default+ ;disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c5|  i2cpclk?default+;okayregulator@42rockchip,rk8602B vdd_npu_s0 dp#~;P*regulator-state-mem[i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c5}  i2cpclk@default+ ;disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c5~  i2cpclkAdefault+ ;disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c5  i2cpclkBdefault+ ;disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !5TW  pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt5dc  tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF5 spiclkapb_pclkt++ytxrx  default+ ;disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG5 spiclkapb_pclkt++ytxrx  default+ ;disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH5 spiclkapb_pclktytxrx default+;okay<L pmic@0rockchip,rk806 defaultB@  ,* 8* D* P* \* h* t* * * *  *   *  dvs1-null-pins gpio_pwrctrl1 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1 vdd_gpu_s0 dp#~;0 regulator-state-mem[dcdc-reg2vdd_cpu_lit_s0 dp#~;0 regulator-state-mem[dcdc-reg3 vdd_log_s0 L# q;0regulator-state-mem[ + qdcdc-reg4 vdd_vdenc_s0 dp#~;0regulator-state-mem[dcdc-reg5 vdd_ddr_s0 L# ;0regulator-state-mem[ + Pdcdc-reg6 vdd2_ddr_s3# regulator-state-mem Gdcdc-reg7vdd_2v0_pldo_s3 #;0regulator-state-mem G +dcdc-reg8 vcc_3v3_s3 2Z#2Zregulator-state-mem G +2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem[dcdc-reg10 vcc_1v8_s3 w@#w@regulator-state-mem G +w@pldo-reg1 avcc_1v8_s0 w@#w@regulator-state-mem[pldo-reg2 vcc_1v8_s0 w@#w@regulator-state-mem[ +w@pldo-reg3 avdd_1v2_s0 O#Oregulator-state-mem[pldo-reg4 vcc_3v3_s0 2Z#2Z;0regulator-state-mem[pldo-reg5 vccio_sd_s0 w@#2Z;0|regulator-state-mem[pldo-reg6 pldo6_s3 w@#w@regulator-state-mem G +w@nldo-reg1 vdd_0v75_s3 q# qregulator-state-mem G + qnldo-reg2vdd_ddr_pll_s0 P# Pregulator-state-mem[ + Pnldo-reg3 avdd_0v75_s0 q# qregulator-state-mem[nldo-reg4 vdd_0v85_s0 P# Pregulator-state-mem[nldo-reg5 vdd_0v75_s0 q# qregulator-state-mem[spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI5 spiclkapb_pclktytxrx  default+ ;disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL5 baudclkapb_pclkt++ ytxrxdefault ;disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM5 baudclkapb_pclkt+ + ytxrxdefault;okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN5 baudclkapb_pclkt+ + ytxrxdefault ;disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO5 baudclkapb_pclkt ytxrxdefault ;disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP5 baudclkapb_pclkt ytxrxdefault ;disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ5 baudclkapb_pclkt ytxrxdefault ;disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR5 baudclkapb_pclkteeytxrxdefault ;disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS5 baudclkapb_pclkte e ytxrxdefault ;disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT5 baudclkapb_pclkte e ytxrxdefault ;disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK  pwmpclkdefault ;disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK  pwmpclkdefault ;disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5LK  pwmpclkdefault ;disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05LK  pwmpclkdefault ;disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON  pwmpclkdefault ;disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON  pwmpclkdefault ;disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5ON  pwmpclkdefault ;disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05ON  pwmpclkdefault ;disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ  pwmpclkdefault ;disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ  pwmpclkdefault ;disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5RQ  pwmpclkdefault ;disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05RQ  pwmpclkdefault ;disabledtsadc@fec00000rockchip,rk3588-tsadc5 tsadcapb_pclk<LVW}tsadc-apbtsadc _ v   gpiootpout ;okayadc@fec10000rockchip,rk3588-saradc 5 saradcapb_pclkU }saradc-apb;okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c5  i2cpclkCdefault+;okayusb-typec@22 fcs,fusb302" default ;okayconnectorusb-c-connector USB-C dual B@ dual d ), 5sourceports+port@0endpointF"port@1endpointFport@2endpointFrtc@51haoyu,hym8563Qhym8563default  Di2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c5  i2cpclkDdefault+ ;disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c5  i2cpclkEdefault+ ;disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ5 spiclkapb_pclkte eytxrx  default+ ;disabledefuse@fecc0000rockchip,rk3588-otp 5 otpapb_pclkphyarb }otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c Rnpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[5p  apb_pclk ephy@fed60000rockchip,rk3588-hdptx-phy 5T refapb8#cde!""}phyapbinitcmnlaneroplllcpll ;disabledphy@fed80000rockchip,rk3588-usbdp-phy5lV refclkimmortalpclkutmi(   }initcmnlanepcs_apbpma_apb W j { ;okay    !port+endpoint@0Fendpoint@1Fphy@fee00000rockchip,rk3588-naneng-combphy5vW  refapbpipe<L<C}phyapb ( ;okayjphy@fee20000rockchip,rk3588-naneng-combphy5xW  refapbpipe<L>E}phyapb ( ;okay'sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank5qr    2gpio@fec20000rockchip,gpio-bank5st    2gpio@fec30000rockchip,gpio-bank5uv  @  2gpio@fec40000rockchip,gpio-bank5wx  `  2kgpio@fec50000rockchip,gpio-bank5yz    2pcfg-pull-up pcfg-pull-down pcfg-pull-none ,pcfg-pull-none-drv-level-2 , 9pcfg-pull-up-drv-level-1  9pcfg-pull-up-drv-level-2  9pcfg-pull-none-smt , Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout ]~emmc-bus8 ]emmc-clk ]emmc-cmd ]emmc-data-strobe ]eth1fspifspim0-pins` ]vgmac1gmac1-miim ]qgmac1-rx-bus20 ] sgmac1-tx-bus20 ]   rgmac1-rgmii-clk ]tgmac1-rgmii-bus@ ]ugpuhdmii2c0i2c0m2-xfer ])i2c1i2c1m0-xfer ]  i2c2i2c2m0-xfer ]  i2c3i2c3m0-xfer ]  i2c4i2c4m0-xfer ]  i2c5i2c5m0-xfer ]  i2c6i2c6m3-xfer ]  i2c7i2c7m0-xfer ]  i2c8i2c8m0-xfer ]  i2s0i2s0-lrck ]i2s0-sclk ]i2s0-sdi0 ]i2s0-sdi1 ]i2s0-sdi2 ]i2s0-sdi3 ]i2s0-sdo0 ]i2s0-sdo1 ]i2s0-sdo2 ]i2s0-sdo3 ]i2s1i2s1m0-lrck ]i2s1m0-sclk ]i2s1m0-sdi0 ]i2s1m0-sdi1 ]i2s1m0-sdi2 ]i2s1m0-sdi3 ]i2s1m0-sdo0 ] i2s1m0-sdo1 ] i2s1m0-sdo2 ] i2s1m0-sdo3 ] i2s2i2s2m1-lrck ]i2s2m1-sclk ] i2s2m1-sdi ] i2s2m1-sdo ] i2s3i2s3-lrck ]i2s3-sclk ]i2s3-sdi ]i2s3-sdo ]jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp ]pmupwm0pwm0m0-pins ]-pwm1pwm1m0-pins ].pwm2pwm2m0-pins ]/pwm3pwm3m0-pins ]0pwm4pwm4m0-pins ] pwm5pwm5m0-pins ] pwm6pwm6m0-pins ] pwm7pwm7m0-pins ] pwm8pwm8m0-pins ] pwm9pwm9m0-pins ] pwm10pwm10m0-pins ] pwm11pwm11m0-pins ] pwm12pwm12m0-pins ] pwm13pwm13m0-pins ] pwm14pwm14m0-pins ] pwm15pwm15m0-pins ] refclksatasata0sata1sata2sdiosdiom1-pins` ]}sdmmcsdmmc-bus4@ ]zsdmmc-clk ]wsdmmc-cmd ]xsdmmc-det ]yspdif0spdif1spi0spi0m0-pins0 ]spi0m0-cs0 ]spi0m0-cs1 ]spi1spi1m1-pins0 ]spi1m1-cs0 ]spi1m1-cs1 ]spi2spi2m2-pins0 ] spi2m2-cs0 ] spi3spi3m1-pins0 ] spi3m1-cs0 ]spi3m1-cs1 ]spi4spi4m0-pins0 ]spi4m0-cs0 ]spi4m0-cs1 ]tsadctsadc-shut ]uart0uart0m1-xfer ] ,uart1uart1m1-xfer ]  uart2uart2m0-xfer ] uart3uart3m1-xfer ]  uart4uart4m1-xfer ]  uart5uart5m1-xfer ]  uart6uart6m1-xfer ]  uart7uart7m1-xfer ]  uart8uart8m1-xfer ]  uart9uart9m1-xfer ]  vopbt656gpio-functsadc-gpio-func ]leds-gpio ]hym8563hym8563-int ]usb-typecusbc0-int ]typec5v-pwren ]chosen kserial2:1500000n8adc-keys adc-keys w buttons w@ dbutton-recovery Recovery h leds gpio-ledsdefaultled-1  status_led heartbeatvbus-typec-regulatorregulator-fixed  kdefault vbus_typec LK@#LK@P*vcc5v0-sys-regulatorregulator-fixed vcc5v0_sys LK@#LK@*vcc-3v3-sd-s0-regulatorregulator-fixed   vcc_3v3_sd_s0 2Z#2ZP{vcc3v3-pcie20-regulatorregulator-fixed  vcc3v3_pcie20 w@#w@ !PP*l compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namesoperating-points-v2power-domainsstatusmali-supplyopp-hzopp-microvoltdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkusb-role-switchremote-endpointsnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerreset-gpiosvpcie3v3-supplyrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyrockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cssystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyvbus-supplylabeldata-roleop-sink-microwattpower-rolesink-pdossource-pdostry-power-rolewakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfmode-switchorientation-switchsbu1-dc-gpiossbu2-dc-gpiosrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codepress-threshold-microvoltlinux,default-triggerenable-active-highgpioenable-active-lowstartup-delay-us