J 8;(;4mediatek,mt8390-evkmediatek,mt8390mediatek,mt8188 +7MediaTek Genio-700 EVKaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dsc@1c009000T/soc/ethdr@1c114000[/soc/mailbox@10320000`/soc/mailbox@10330000e/soc/merge0@1c014000l/soc/merge@1c10c000s/soc/merge@1c10d000z/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000/soc/rdma@1c107000/soc/rdma@1c108000/soc/rdma@1c109000'/soc/rdma@1c10a0002/soc/rdma@1c10b000=/soc/dsi@1c008000B/soc/ethernet@11021000L/soc/i2c@11280000Q/soc/i2c@11e00000V/soc/i2c@11281000[/soc/i2c@11282000`/soc/i2c@11e01000e/soc/i2c@11ec0000j/soc/i2c@11ec1000o/soc/mmc@11230000t/soc/mmc@11240000y/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psciw5@ @*;O^ cpu@100cpuarm,cortex-a55psciw5@ @*;O^ cpu@200cpuarm,cortex-a55psciw5@ @*;O^ cpu@300cpuarm,cortex-a55psciw5@ @*;O^ cpu@400cpuarm,cortex-a55psciw5@ @*;O^ cpu@500cpuarm,cortex-a55psciw5@ @*;O^cpu@600cpuarm,cortex-a78psci@ @*;O^cpu@700cpuarm,cortex-a78psci@ @*;O^cpu-mapcluster0core0f core1f core2f core3f core4f core5fcore6fcore7fidle-statesjpscicpu-off-larm,idle-statew2_D^cpu-off-barm,idle-statew-^cluster-off-larm,idle-statew7H^cluster-off-barm,idle-statew2^l2-cache0cache@*^l2-cache1cache@*^l3-cachecache @^oscillator-13m fixed-clock]@clk13m^9oscillator-26m fixed-clockclk26m^;oscillator-32k fixed-clockclk32kopp-table-gpuoperating-points-v2 ^opp-390000000>+opp-431000000+opp-4730000001h@ '+opp-515000000F X+opp-556000000!# h+opp-598000000# <+opp-640000000&% +opp-670000000'c +opp-700000000)' L+opp-730000000+ }+opp-760000000-L `+opp-790000000/q 4+opp-8350000001 (r+opp-8800000004s q+opp-9150000006 X+opp-915000000-56 +0opp-915000000-66 q+popp-9500000008ـ 5+opp-950000000-58ـ X+0opp-950000000-68ـ q+ppmu-a55arm,cortex-a55-pmu <pmu-a78arm,cortex-a78-pmu <psci arm,psci-1.0smcsoundGYokay6mediatek,mt8390-mt6359-evkmediatek,mt8188-mt6359-evb 7mt8390-evk`defaultntxHeadphoneHeadphone LHeadphoneHeadphone RDMIC_INPUTAP DMICAP DMICAUDGLBAP DMICMIC_BIAS_0AP DMICMIC_BIAS_2dai-link-0 DL_SRC_BEcodecdai-link-1DMIC_BEcodecthermal-zonescpu-little0-thermaltripstrip-alert0Lpassive^trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little1-thermaltripstrip-alert0Lpassive^trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little2-thermaltripstrip-alert0Lpassive^trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-little3-thermaltripstrip-alert0Lpassive^trip-alert1shottrip-crit criticalcooling-mapsmap0H cpu-big0-thermaldtripstrip-alert0Lpassive^trip-alert1shottrip-crit criticalcooling-mapsmap0cpu-big1-thermaldtripstrip-alert0Lpassive^trip-alert1shottrip-crit criticalcooling-mapsmap0apu-thermal tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalgpu-thermal tripstrip-alert0Lpassive^!trip-alert1shottrip-crit criticalcooling-mapsmap0! "gpu1-thermal tripstrip-alert0Lpassive^#trip-alert1shottrip-crit criticalcooling-mapsmap0# "adsp-thermal tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalvdo-thermal tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalinfra-thermal tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalcam1-thermal tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticalcam2-thermal tripstrip-alert0Lpassivetrip-alert1shottrip-crit criticaltimerarm,armv8-timer @<   ]@soc+ simple-bus performance-controller@11bc10mediatek,cpufreq-hw  0 ^interrupt-controller@c000000 arm,gic-v3,= T    < ^ppi-partitionsinterrupt-partition-0i ^interrupt-partition-1i^syscon@10000000 mediatek,mt8188-topckgensyscon^'syscon@10001000#mediatek,mt8188-infracfg-aosysconr^(syscon@10003000mediatek,mt8188-pericfgsyscon0^Kpinctrl@10005000mediatek,mt8188-pinctrl`P0iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint$T<,^$audio-default-pins^pins-cmd-datXefghijklmnrstuvyz|}~disp-pwm1-pins^Gpins-pwmdptx-pinspins-cmd-dat.edp-panel-3v3-en-pins^pins1eth-default-pins^Wpins-ccpins-mdiopins-powerpins-rxdpins-txdeth-sleep-pins^Xpins-ccpins-mdiopins-rxdpins-txdi2c0-pins^bpins87i2c1-pins^tpins:9i2c2-pins^fpins<;i2c3-pins^gpins>=i2c4-pins^wpins@?i2c5-pins^~pinsBAi2c6-pins^pinsDCgpio-key-pinspins *+,mmc0-default-pins^Ypins-clk fpins-cmd-dat$epins-rstemmc0-uhs-pins^Zpins-clk fpins-cmd-dat$epins-ds fpins-rstemmc1-default-pins^]pins-clk fpins-cmd-datepins-insertmmc1-uhs-pins^^pins-clk fpins-cmd-datemmc2-default-pinspins-clk fpins-cmd-datepins-pcm{mmc2-uhs-pinspins-clk fpins-cmd-datemmc2-eint-pinspins-dat1emmc2-dat1-pinspins-dat1edsi0-vreg-en-pins^pins-pwr-eno/panel-default-pins^pins-rst/pins-en-/pcie-default-pins^rpins /01rt1715-int-pinspins_cmd0_dat spi0-pinspins-spiEFGHspi1-pinspins-spiKLMNspi2-pins^Hpins-spiOPQRtouch-avdd-pins^pins-powerxtouch-pins^epins-irqpins-resettcpci-int-pins^xpins-int-n uart0-pins^Cpins uart1-pins^Dpins!"uart2-pins^Epins#$usb-default-pins^mpins-iddigSpins-validUpins-vbusTusb1-default-pins^Mpins-validXpins-usb-hub-3v3-enpusb2-default-pins^ipins-iddigYwifi-pwrseq-pinspins-wifi-enable/syscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfd`power-controller!mediatek,mt8188-power-controller+:^<power-domain@0+:N%power-domain@1\&'cmfgalto(+:N)power-domain@2:power-domain@3:power-domain@4:power-domain@15\'''' '3'4'=''* * ***************** ctopcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1o(+:power-domain@16H\''+++++++Accfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-buso(+:power-domain@200\'',,,,8ccfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6o(:power-domain@22\-css-vdec1-soc-l1o(+:power-domain@23\. css-vdec2-l1o(:power-domain@29 \''' 'ccamccubuscfgcko(+:power-domain@30(\/////6css-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsyso(+:power-domain@32 \/01$css-camb-subss-camb-rawss-camb-yuv:power-domain@31\/23$css-cama-subss-cama-rawss-cama-yuv:power-domain@17(\''444&ccfgckcfgxoss-larb2ss-larb3ss-galso(+:power-domain@9 \'@'? cbushdcpo(:power-domain@18o(:power-domain@19o(:power-domain@24 \55550css-ve1-larbss-ve1-coress-ve1-galsss-ve1-sramo(:power-domain@21\66css-wpe-l7ss-wpe-l7pceo(:power-domain@5o(\7 css-pextp-fmem:power-domain@7\'0'1cseninf0seninf1:power-domain@6:power-domain@10 \'E'D cbusmaino(+:power-domain@11 o(+:power-domain@14\'Fcasmo(:power-domain@13 \'S'8ca1sysintbusadspcko(:power-domain@12 o(:power-domain@8\7  cethermaco(:watchdog@10007000mediatek,mt8188-wdtpr^=syscon@1000c000"mediatek,mt8188-apmixedsyssyscon^&timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerp< \9pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscon@pwrap<\(( cspiwrappmicmediatek,mt6359T, $<^adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5 !#?buck_vgpu11 dvdd_core 7S# h?buck_vmodemvmodem S*#buck_vpu dvdd_adsp 7S# h?buck_vcore dvdd_proc_l  S# h?buck_vs2vs2 5 j#?buck_vpavpa_pmu  /M`#,^_buck_vproc2vgpudp 5SL# h)j^%buck_vproc1vproc1 7SL# hbuck_vcore_sshub vcore_sshub 7buck_vgpu11_sshub vgpu11_sshub 7ldo_vaud18vaud18w@ w@#ldo_vsim1 vsim1_pmu /M`#^`ldo_vibrvibrO 2Zldo_vrf12va12_abb2_pmu  ?ldo_vusbvusb- -#?^Lldo_vsram_proc2 vsram_proc2  SL#?ldo_vio18vio18 #?^dldo_vcamiovcamio ldo_vcn18 vcn18_pmuw@ w@#?ldo_vfe28vfe28* *#xldo_vcn13vcn13   ldo_vcn33_1_bt vcn33_1_bt* 5g^uldo_vcn33_1_wifi vcn33_1_wifi* 5gldo_vaux18vaux18w@ w@#?ldo_vsram_others vsram_gpu q 5S#%j^)ldo_vefusevefuse ldo_vxo22vxo22w@ !?ldo_vrfckvrfck` ldo_vrfck_1vrfck jldo_vbif28vbif28* *#ldo_vio28vio28* 2Z?ldo_vemcvemc,@  2Zldo_vemc_1vemc&% 2Z^[ldo_vcn33_2_bt vcn33_2_pmu* 5g?ldo_vcn33_2_wifi vcn33_2_wifi* 5gldo_va12va12O  ?ldo_va09va09 5 Oldo_vrf18vrf18 Pldo_vsram_md vsram_md  S*#ldo_vufs vufs18_pmu ?^\ldo_vm18vm18 ?ldo_vbbckvbbck O?ldo_vsram_proc1 vsram_proc1  SL#?ldo_vsim2vsim2 /M`ldo_vsram_others_sshubvsram_others_sshub  rtcmediatek,mt6358-rtckeysmediatek,mt6359-keyspower-keytspmi@10027000*mediatek,mt8188-spmimediatek,mt8195-spmi p pmifspmimst'8 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cbaudbusYokaynC`defaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uart< \;( cbaudbusYokaynD`defaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uart< \;( cbaudbusYokaynE`defaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uart< \;( cbaudbus Ydisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc \(cmain Ydisabledsyscon@11003000"mediatek,mt8188-pericfg-aosyscon0^7spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+<\'y'(cparent-clksel-clkspi-clk Ydisabledthermal-sensor@1100b000mediatek,mt8188-lvts-ap <\(Y(Flvts-calib-data-1^ pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm\''(/cmainmm< Ydisabledpwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm\'((Fcmainmm<Yokay`defaultnG^spi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+<\'y'(2cparent-clksel-clkspi-clk Ydisabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ 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'v\7csys_ckYokayL 0jconnector%gpio-usb-b-connectorusb-b-connectormicro <$Y 0kusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> macippc +?+<', 'v\7'7csys_ckref_ckmcu_ckl K`Yokayotg high-speedLnm`defaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimac<'+ 'v\7csys_ckYokayconnector%gpio-usb-b-connectorusb-b-connectormicro <$S 0npcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  pcie-mac  Epci O+0\(L(#(&(+(C7 /cpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem,<` `oooo n p q pcie-phyK<Y=`macYokay`defaultnrinterrupt-controller,T^ospi@1132c000(mediatek,mt8188-normediatek,mt8186-nor2\'X77 cspisfaxi'X<9+ Ydisabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3 +K<Yokaypcie-phy@0\'cref ^qdsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx\; mipi_tx0_pll Yokay^dsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx\; mipi_tx0_pll  Ydisabled^i2c@11e00000mediatek,mt8188-i2c "< \s(7 cmaindma+Yokay`defaultnttypec-mux@48 ite,it5205H   uportendpointDv^|i2c@11e01000mediatek,mt8188-i2c "< \s(7 cmaindma+Yokay`defaultnwB@rt1715@4erichtek,rt1715N $ `defaultnx 0yconnectorusb-c-connector USB-C dual  dual sink  !" +"altmodesdisplayport 7 <Gports+port@0endpointDz^Rport@1endpointD{^Qport@2endpointD|^vclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w ^st-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ Yokayusb-phy@0\'& crefda_ref ^lt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ Yokayusb-phy@0\'& crefda_ref ^Iusb-phy@700 \&; crefda_ref ^Jt-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ Yokayusb-phy@0\'& crefda_ref ^hi2c@11ec0000mediatek,mt8188-i2c "< \}(7 cmaindma+Yokay`defaultn~i2c@11ec1000mediatek,mt8188-i2c "< \}(7 cmaindma+Yokay`defaultnclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en ^}efuse@11f20000%mediatek,mt8188-efusemediatek,efuse+dp-calib@1a0 ^lvts1-calib@1ac@^Fgpu-speedbin@581 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display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot x\* K<   +mutex@1400f000mediatek,mt8188-vpp-mutex<P\*K< smi@14012000mediatek,mt8188-smi-common-vpp \**capbsmiK<^smi@14013000mediatek,mt8188-smi-larb0\**capbsmiK<  ^iommu@14018000mediatek,mt8188-iommu-vppP\*cbclk<RK<$ ^dma-controller@14f09000mediatek,mt8188-mdp3-rdma x\,  K<  dma-controller@14f0a000mediatek,mt8188-mdp3-rdma x\,  K<  display@14f0c0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg\,  display@14f0d0000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg\,  display@14f0f0002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr\," display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr\,$ display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal <j\,#K< display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal0<k\,%K< 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rszP\, P display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`\, ` display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp\, display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp\, display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge\,K< display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge\,K< display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color<u\,K< display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color<v\,K< display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding\,K< display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding \,K< display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot@ x\, K< @ display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrotP x\, K< P clock-controller@14e00000mediatek,mt8188-wpesys^6clock-controller@14e02000mediatek,mt8188-wpesys-vpp0 smi@14e04000mediatek,mt8188-smi-larb@\66capbsmiK<  ^syscon@14f00000mediatek,mt8188-vppsys1syscon^,mutex@14f01000mediatek,mt8188-vpp-mutex<{\,&K< smi@14f02000mediatek,mt8188-smi-larb \,,capbsmiK<  ^smi@14f03000mediatek,mt8188-smi-larb0\,,capbsmiK<  ^clock-controller@15000000mediatek,mt8188-imgsysclock-controller@15110000 mediatek,mt8188-imgsys1-dip-toprclock-controller@15130000mediatek,mt8188-imgsys1-dip-nrrclock-controller@15220000mediatek,mt8188-imgsys-wpe1"rclock-controller@15330000mediatek,mt8188-ipesys3rclock-controller@15520000mediatek,mt8188-imgsys-wpe2Rrclock-controller@15620000mediatek,mt8188-imgsys-wpe3brclock-controller@16000000mediatek,mt8188-camsys^/clock-controller@1604f000mediatek,mt8188-camsys-rawar^2clock-controller@1606f000mediatek,mt8188-camsys-yuvar^3clock-controller@1608f000mediatek,mt8188-camsys-rawbr^0clock-controller@160af000mediatek,mt8188-camsys-yuvb r^1clock-controller@17200000mediatek,mt8188-ccusys video-decoder@18000000mediatek,mt8188-vcodec-dec @ ` + video-codec@10000mediatek,mtk-vcodec-lat'4 'x \'4--'xcselvdeclattop<H K<video-codec@25000mediatek,mtk-vcodec-coreP'4 'x \'4..'xcselvdeclattop<X K<smi@1800d000mediatek,mt8188-smi-larb\--capbsmiK<  ^clock-controller@1800f000mediatek,mt8188-vdecsys-soc^-smi@1802e000mediatek,mt8188-smi-larb\..capbsmiK<  ^clock-controller@1802f000mediatek,mt8188-vdecsys^.clock-controller@1a000000mediatek,mt8188-vencsys^5smi@1a010000mediatek,mt8188-smi-larb\55capbsmiK<  ^video-encoder@1a020000mediatek,mt8188-vcodec-enc+'3 'p\5 cvenc_sel<aX K< jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc\5cjpgenc<b K<jpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec\55cjpgdec-smijpgdec<c0 K<ovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl\+<| K< ports+port@0endpointD^port@1endpointD^rdma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma \+<~ K<  ports+port@0endpointD^port@1endpointD^color@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color0\+<K< 0ports+port@0endpointD^port@1endpointD^ccorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr@\+<K< @ports+port@0endpointD^port@1endpointD^aal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aalP\+ <K< Pports+port@0endpointD^port@1endpointD^gamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma`\+<K< `ports+port@0endpointD^port@1endpointD^dither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-ditherp\+<K< pports+port@0endpointD^port@1endpointD^dsi@1c008000mediatek,mt8188-dsi\++cenginedigitalhs< dphyK<Y+Yokay+panel@0#startek,kd070fhfid078himax,hx8279  $- -$ 9`defaultnportendpointD^ports+port@0endpointD^port@1endpointD^dsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc\+ <K< dsi@1c012000mediatek,mt8188-dsi \+ +cenginedigitalhs< dphyK<Y+  Ydisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge@\+ 4cmergemerge_async<K< @dp-intf@1c015000mediatek,mt8188-dp-intfP\+ + &cpixelenginepll<K< Ydisabledmutex@1c016000mediatek,mt8188-disp-mutex`\+<K< ` >postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask\+<K< ports+port@0endpointD^port@1endpointD^syscon@1c01d000mediatek,mt8188-vdosys0sysconr ~ ^+port+endpoint@0D^smi@1c022000mediatek,mt8188-smi-larb \++capbsmiK<  ^smi@1c023000mediatek,mt8188-smi-larb0\++capbsmiK<  ^smi@1c024000mediatek,mt8188-smi-common-vdo@\++capbsmiK<^iommu@1c028000mediatek,mt8188-iommu-vdoP\+cbclk<K<$ ^syscon@1c100000mediatek,mt8188-vdosys1sysconr ~ ^4mutex@1c101000mediatek,mt8188-disp-mutex\4<K<  smi@1c102000mediatek,mt8188-smi-larb \44capbsmiK<  ^smi@1c103000mediatek,mt8188-smi-larb0\44capbsmiK<  ^rdma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma@\4< @K< x @rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmaP\4< `K< x Prdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma`\4< AK< x `rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdmap\4< aK< x prdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma\4< BK< x rdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma\4< bK< x rdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma\4< CK< x rdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma\4< cK< x merge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge\4 4cmergemerge_async<K<Y4  merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge\4 4cmergemerge_async<K<Y4  merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge\4 4cmergemerge_async<K<Y4  merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge\4 4cmergemerge_async<K<Y4  merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge\4 4cmergemerge_async<K<Y4  (dp-intf@1c113000mediatek,mt8188-dp-intf0\4:4&cpixelenginepll<K< Ydisabledethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh\404+4.4,4/4-4<4142434445'cmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top<6 deK<(Y4142434445p @Pppadding@1c11d000mediatek,mt8188-disp-padding\4K< padding@1c11e000mediatek,mt8188-disp-padding\4 K< padding@1c11f000mediatek,mt8188-disp-padding\4!K< padding@1c120000mediatek,mt8188-disp-padding\4"K< padding@1c121000mediatek,mt8188-disp-padding\4#K< padding@1c122000mediatek,mt8188-disp-padding \4$K<  padding@1c123000mediatek,mt8188-disp-padding0\4%K< 0padding@1c124000mediatek,mt8188-disp-padding@\4&K< @edp-tx@1c500000mediatek,mt8188-edp-txP<dp_calibration_dataK< ? Ydisableddp-tx@1c600000mediatek,mt8188-dp-tx`<dp_calibration_dataK< ? Ydisabledbacklight-lcm1pwm-backlight P b@ {   ^chosen serial0:921600n8dmic-codec dmic-codec  ^firmwareopteelinaro,optee-tzsmcreserved-memory+ optee@43200000 C memory@50000000shared-dma-poolP ^:memory@54600000 T` memory@55000000shared-dma-poolU@memory@57000000shared-dma-poolW@memory@60000000shared-dma-pool` ^Bmemory@60f00000shared-dma-pool` ^>memory@61000000shared-dma-poola ^Aregulator-0regulator-fixedvdd_5vLK@ LK@ $  ? regulator-1regulator-fixed vedp_3v32Z 2Z  $`defaultn regulator-2regulator-fixedext_3v32Z 2Z $  ? regulator-vsysregulator-fixedvsys? ^regulator-3regulator-fixed vio18_connw@ w@ ?regulator-4regulator-fixed wifi_3v32Z 2Z $J ? ^jregulator-5regulator-fixed vio33_tp12Z 2Z $w  `defaultn^cregulator-6regulator-fixed vhub_3v32Z 2Z $p'  ^Oregulator-7regulator-fixedvbus_p0LK@ LK@ $T  ^nregulator-8regulator-fixedvbus_p1LK@ LK@ $W  ^yregulator-9regulator-fixedvbus_p2LK@ LK@ ^kregulator-vio18-lcm1regulator-fixed vio18_lcm1w@ w@  $o`defaultn ^regulator-vsys-lcm1regulator-fixed vsys_lcm1@@ @@?  ^memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0ethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0mmc1serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0audio-routingmediatek,adsplink-namesound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upoutput-highdrive-strengthinput-enableinput-disablebias-disabledrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cells#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadmediatek,long-press-modepower-off-time-seclinux,keycodeswakeup-sourceassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellsmemory-regionpower-domainsresetsreset-namesmediatek,topckgenmboxesmbox-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectphysmediatek,syscon-wakeupdr_modeusb-role-switchvusb33-supplypeer-hubreset-gpiosvdd-supplyremote-endpointinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolsnps,reset-gpiosnps,reset-delays-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmccd-gpiosclock-divinterrupts-extendedirq-gpiosAVDD28-supplyVDDIO-supplymaximum-speedrole-switch-default-modevbus-supplyid-gpiosbus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsmode-switchorientation-switchvcc-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolepd-revisionsink-pdossource-pdossvidvdobitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsbacklightenable-gpiosiovcc-supplymediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msno-mapenable-active-highvin-supplyregulator-boot-onstartup-delay-us