e8X( X`4mediatek,mt8395-evkmediatek,mt8395mediatek,mt8195 +"7MediaTek Genio 1200 EVK-P1V2-EMMCaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/serial@11001100/soc/ethernet@11021000cpus+cpu@0cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@100cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@200cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@300cpuarm,cortex-a55 psci-ec3@=4P`m@@ cpu@400cpuarm,cortex-a78 psci-f=P`m@@ cpu@500cpuarm,cortex-a78 psci-f=P`m@@cpu@600cpuarm,cortex-a78 psci-f=P`m@@cpu@700cpuarm,cortex-a78 psci-f=P`m@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state2*_:Dcpu-retention-barm,idle-state-*:cpu-off-larm,idle-state7*:Hcpu-off-barm,idle-state2*:l2-cache0cacheKbo@Wl2-cache1cacheKbo@Wl3-cachecacheKb o@Wdsu-pmu arm,dsu-pmue p ufaildmic-codec dmic-codec|mt8195-sound udisabledfixed-factor-clock-13mfixed-factor-clockclk13m*oscillator-26m fixed-clock-clk26moscillator-32k fixed-clock-clk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 opp-table-gpuoperating-points-v2xopp-390000000 > hopp-410000000 p opp-431000000  opp-473000000 1h@ <opp-515000000 F <opp-556000000 !# Ҧopp-598000000 # opp-640000000 &% opp-670000000 'c opp-700000000 )' Lopp-730000000 + }opp-760000000 -L `opp-790000000 /q 4opp-820000000 05 opp-850000000 2 @opp-880000000 4s qpmu-a55arm,cortex-a55-pmu epmu-a78arm,cortex-a78-pmu epsci arm,psci-1.0smctimerarm,armv8-timer @e   soc+ simple-bus!(interrupt-controller@c000000 arm,gic-v33D [    e ppi-partitionsinterrupt-partition-0p interrupt-partition-1p syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000#mediatek,mt8195-infracfg_aosysconysyscon@10003000mediatek,mt8195-pericfgsyscon0Cpinctrl@10005000mediatek,mt8195-pinctrlPBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint[e3audio-default-pinspins-cmd-dat4=>ABCDEFGHIJKdisp-pwm1-default-pinspins1hedp-panel-12v-en-pinspins1`edp-panel-3v3-en-pinspins1eth-default-pins?pins-ccUVWXpins-mdioYZpins-power[\pins-rxdQRSTpins-txdMNOPeth-sleep-pins@pins-ccUVWXpins-mdioYZpins-rxdQRSTpins-txdMNOPgpio-keys-pinspinsji2c0-pinscpins i2c1-pinsdpins  i2c2-pinsgpins  i2c6-pins\pinsmmc0-default-pinsHpins-clkz'fpins-cmd-dat$~}|{wvutyepins-rstxemmc0-uhs-pinsIpins-clkz'fpins-cmd-dat$~}|{wvutyepins-ds'fpins-rstxemmc1-default-pinsLpins-clko'fpins-cmd-datnpqrsemmc1-uhs-pinsMpins-clko'fpins-cmd-datnpqrsemt6360-pins]pinsdsi0-vreg-en-pinspins-pwr-en/6panel-default-pinspins-rstlpins-en06pcie0-default-pinsWpins pcie0-idle-pinsXpins6pcie1-default-pinsZpins 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udisabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbusuokayI1Sdefaultserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbusuokayI2Sdefaultserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uarte  cbaudbus udisabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc cmain udisabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0)spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+ecparent-clksel-clkspi-clk udisabledthermal-sensor@1100b000mediatek,mt8195-lvts-ap e6a34$mlvts-calib-data-1lvts-calib-data-2~svs@1100bc00mediatek,mt8195-svsecmaina53(msvs-calibration-datat-calibration-data6=svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwme-*0cmainmmuokaySdefaultI6pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwme+Ncmainmm udisabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+e3cparent-clksel-clkspi-clkuokayI7Sdefault @can@0microchip,mcp2518fd81- 99spi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ e4cparent-clksel-clkspi-clkuokayI:Sdefaultspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0e5cparent-clksel-clkspi-clk udisabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+e<cparent-clksel-clkspi-clk udisabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+e=cparent-clksel-clkspi-clk udisabledspi@1101d000mediatek,mt8195-spi-slaveeRcspi udisabledspi@1101e000mediatek,mt8195-spi-slaveeScspi udisabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a@emacirq.caxiapbmac_mainptp_refrmii_internalmac_cg0))RST) RST- ;<,=?JUuokay brgmii-rxidk> v] ''SdefaultsleepI?@mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916>stmmac-axi-config;rx-queues-config <queue0/queue1/queue2/queue3/tx-queues-configG]=queue0o{queue1o{queue2o{queue3o{usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3  - > macippc! ?+e/Bcsys_ckref_ckmcu_ckAB CguokayotgSdefaultIDEusb@0'mediatek,mt8195-xhcimediatek,mtk-xhcimace,-$/B$csys_ckref_ckmcu_ckdma_ckxhci_ckuokayports+port@0endpointF_port@1endpointG`mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #ecsourcehclksource_cguokaySdefaultstate_uhsIHI    # 4 < BL QJ ]K jmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $e$csourcehclksource_cguokaySdefaultstate_uhsILM  x    4 QN ]O jmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %e Icsourcehclksource_cg  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T 0V#&+K)/cpl_250mtl_26mtl_96mtl_32kperi_26mperi_memGU pcie-phy-6=mac3 ` VVVVuokay SdefaultidleIWXinterrupt-controller[3Vpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+/@ pcie-mace 8!$$ $ $  T (WXQ)/cpl_250mtl_26mtl_96mtl_32kperi_26mperi_memHQ pcie-phy-3 ` YYYY udisabledSdefaultIZinterrupt-controller[3Yspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2e9o)) cspisfaxi+ udisabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1 ousb3-rx-imp@184,2 nusb3-intr@185 musb3-tx-imp@186,1 lusb3-rx-imp@186,2 kusb3-intr@187 jusb2-intr-p0@188,1 usb2-intr-p1@188,2 usb2-intr-p2@189,1 usb2-intr-p3@189,2 pciephy-rx-ln1@190,1 vpciephy-tx-ln1-nmos@190,2 upciephy-tx-ln1-pmos@191,1 tpciephy-rx-ln0@191,2 spciephy-tx-ln0-nmos@192,1 rpciephy-tx-ln0-pmos@192,2 qpciephy-glb-intr@193 pdp-data@1aclvts1-calib@1bc3lvts2-calib@1d084svs-calib@580d5socinfo-data1@7a0t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0cref Rt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0cref Sdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx0_pll uokaydsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx mipi_tx1_pll  udisabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "e[; cmaindma+ udisabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "e[; cmaindma+uokay-I\Sdefaultpmic@34mediatek,mt63604 eIRQB[3I]chargermediatek,mt6360-chg @usb-otg-vbus-regulator 3usb-otg-vbusBC(ZXregulatormediatek,mt6360-regulator "^buck1 3emi_vdd2BZ  buck2 3emi_vddqBZ  ^ldo1 3tp1_p3v0B2ZZ2Zeldo2 3panel1_p1v8Bw@Zw@ldo33vmc_pmuBOZ6Oldo5 3vmch_pmuB)2Z6Nldo6 3mt6360_ldo1B Z ldo7 3emi_vmddr_enB Z tcpcmediatek,mt6360-tcpc PD_IRQBconnectorusb-c-connector 2USB-C 8dual B Tdual _sink n"d z" altmodesdisplayport  Fports+port@0endpoint_Fport@1endpoint`Gport@2endpointaii2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "e[; cmaindma+ udisabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0[i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eb; cmaindma+uokay-IcSdefaulti2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "eb; cmaindma+uokay-IdSdefaulttouchscreen@5dgoodix,gt9271]    eSdefaultIfi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "eb; cmaindma+uokay-IgSdefaulttypec-mux@48 ite,it5205H h  uokayportendpointiai2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"eb; cmaindma+ udisabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"eb; cmaindma+ udisabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wPbt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!-uokayusb-phy@0  crefda_ref Pusb-phy@700 crefda_ref ajklmintrrx_imptx_imp  Qt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+!uokayusb-phy@0  crefda_ref Ausb-phy@700 crefda_ref amnomintrrx_imptx_imp Bphy@11e80000mediatek,mt8195-pcie-physifapqrstuvGmglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1- uokayUufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy cunipromp  udisabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm@w0e jobmmugpu x(- - - - - core0core1core2core3core4uokay "clock-controller@13fbf000mediatek,mt8195-mfgcfgwsyscon@14000000mediatek,mt8195-vppsys0syscon .ydma-controller@14001000mediatek,mt8195-mdp3-rdma .y F  Zz- g{<y y yyy ndisplay@14002000mediatek,mt8195-mdp3-fg  .y display@14003000mediatek,mt8195-mdp3-stitch0 .y0display@14004000mediatek,mt8195-mdp3-hdr@ .y@"display@14005000mediatek,mt8195-mdp3-aalPeF .yP -display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` .y` F% display@14007000mediatek,mt8195-mdp3-tdshpp .yp#display@14008000mediatek,mt8195-mdp3-coloreI .y$-display@14009000mediatek,mt8195-mdp3-ovleJ .y%- g{display@1400a000mediatek,mt8195-mdp3-padding .y-display@1400b000mediatek,mt8195-mdp3-tcc .ydma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot .y F + g{- nmutex@1400f000mediatek,mt8195-vpp-mutexeP .y-smi@14010000mediatek,mt8195-smi-sub-commoncapbsmigals0 y|-}smi@14011000mediatek,mt8195-smi-sub-commoncapbsmigals0 y|-smi@14012000mediatek,mt8195-smi-common-vpp  capbsmigals0gals1-|larb@14013000mediatek,mt8195-smi-larb0  y}capbsmi-iommu@14018000mediatek,mt8195-iommu-vpp8 ~eRcbclk-{clock-controller@14e00000mediatek,mt8195-wpesysclock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@  ycapbsmi-larb@14e05000mediatek,mt8195-smi-larbP  y| capbsmigals-syscon@14f00000mediatek,mt8195-vppsys1syscon .y mutex@14f01000mediatek,mt8195-vpp-mutexe{ .y '-larb@14f02000mediatek,mt8195-smi-larb   y capbsmigals-larb@14f03000mediatek,mt8195-smi-larb0  y} capbsmigals-display@14f06000mediatek,mt8195-mdp3-split` .y `+,-display@14f07000mediatek,mt8195-mdp3-tccp .y pdma-controller@14f08000mediatek,mt8195-mdp3-rdma .y  F g- ndma-controller@14f09000mediatek,mt8195-mdp3-rdma .y  F  g- ndma-controller@14f0a000mediatek,mt8195-mdp3-rdma .y  F  g{- ndisplay@14f0b000mediatek,mt8195-mdp3-fg .y  display@14f0c000mediatek,mt8195-mdp3-fg .y  display@14f0d000mediatek,mt8195-mdp3-fg .y  display@14f0e000mediatek,mt8195-mdp3-hdr .y display@14f0f000mediatek,mt8195-mdp3-hdr .y display@14f10000mediatek,mt8195-mdp3-hdr .y  display@14f11000mediatek,mt8195-mdp3-aalei .y -display@14f12000mediatek,mt8195-mdp3-aal ej .y -display@14f13000mediatek,mt8195-mdp3-aal0ek .y 0!-display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz@ .y @ Fdisplay@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rszP .y P F$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz` .y ` F%display@14f17000mediatek,mt8195-mdp3-tdshpp .y pdisplay@14f18000mediatek,mt8195-mdp3-tdshp .y (display@14f19000mediatek,mt8195-mdp3-tdshp .y )display@14f1a000mediatek,mt8195-mdp3-merge .y -display@14f1b000mediatek,mt8195-mdp3-merge .y -display@14f1c000mediatek,mt8195-mdp3-coloret .y -display@14f1d000mediatek,mt8195-mdp3-color .y eu-display@14f1e000mediatek,mt8195-mdp3-colorev .y -display@14f1f000mediatek,mt8195-mdp3-ovlew .y - gdisplay@14f20000mediatek,mt8195-mdp3-padding .y -display@14f21000mediatek,mt8195-mdp3-padding .y -display@14f22000mediatek,mt8195-mdp3-padding  .y -dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot0 .y 0 F g- ndma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot@ .y @ F g- ndma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrotP .y P F g{- nclock-controller@15000000mediatek,mt8195-imgsys&larb@15001000mediatek,mt8195-smi-larb  y&&&  capbsmigals-smi@15002000mediatek,mt8195-smi-sub-common &&capbsmigals0 y|-smi@15003000mediatek,mt8195-smi-sub-common0&&& capbsmigals0 y-clock-controller@15110000 mediatek,mt8195-imgsys1_dip_toplarb@15120000mediatek,mt8195-smi-larb  y&capbsmi-clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"larb@15230000mediatek,mt8195-smi-larb#  y&capbsmi-clock-controller@15330000mediatek,mt8195-ipesys3'larb@15340000mediatek,mt8195-smi-larb4  y''capbsmi-clock-controller@16000000mediatek,mt8195-camsys(larb@16001000mediatek,mt8195-smi-larb  y((( capbsmigals-larb@16002000mediatek,mt8195-smi-larb   y((capbsmi-smi@16004000mediatek,mt8195-smi-sub-common@(((capbsmigals0 y-smi@16005000mediatek,mt8195-smi-sub-commonP((capbsmigals0 y|-larb@16012000mediatek,mt8195-smi-larb   ycapbsmi- larb@16013000mediatek,mt8195-smi-larb0  ycapbsmi- larb@16014000mediatek,mt8195-smi-larb@  ycapbsmi-!larb@16015000mediatek,mt8195-smi-larbP  ycapbsmi-!clock-controller@1604f000mediatek,mt8195-camsys_rawaclock-controller@1606f000mediatek,mt8195-camsys_yuvaclock-controller@1608f000mediatek,mt8195-camsys_rawbclock-controller@160af000mediatek,mt8195-camsys_yuvb clock-controller@16140000mediatek,mt8195-camsys_mrawlarb@16141000mediatek,mt8195-smi-larb  y(( capbsmigals-"larb@16142000mediatek,mt8195-smi-larb   ycapbsmi-"clock-controller@17200000mediatek,mt8195-ccusys larb@17201000mediatek,mt8195-smi-larb   ycapbsmi-video-codec@18000000mediatek,mt8195-vcodec-dec Zz g+ @!`video-codec@2000mediatek,mtk-vcodec-lat-soc  g{{ A  cselvdeclattopA-video-codec@10000mediatek,mtk-vcodec-late0 g A  cselvdeclattopA-video-codec@25000mediatek,mtk-vcodec-corePeP g A!!cselvdeclattopA-larb@1800d000mediatek,mt8195-smi-larb  y capbsmi-larb@1800e000mediatek,mt8195-smi-larb  y capbsmi-clock-controller@1800f000mediatek,mt8195-vdecsys_soc larb@1802e000mediatek,mt8195-smi-larb  y!!capbsmi-clock-controller@1802f000mediatek,mt8195-vdecsys!larb@1803e000mediatek,mt8195-smi-larb  y"capbsmi-clock-controller@1803f000mediatek,mt8195-vdecsys_core1"clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsys#larb@1a010000mediatek,mt8195-smi-larb  y##capbsmi-video-codec@1a020000mediatek,mt8195-vcodec-encH g`abcdvwxyeU Zz# cvenc_sel@-+jpgdec-mastermediatek,mt8195-jpgdec-0 gmnrstu+!jpgdec@1a040000mediatek,mt8195-jpgdec-hw0 gmnrstueW#cjpgdec-jpgdec@1a050000mediatek,mt8195-jpgdec-hw0 gmnrstueX#cjpgdec-jpgdec@1b040000mediatek,mt8195-jpgdec-hw0 g{{{{{{e\$cjpgdec-clock-controller@1b000000mediatek,mt8195-vencsys_core1$syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon  .port+endpoint@0jpgenc-mastermediatek,mt8195-jpgenc- g{{{{+!jpgenc@1a030000mediatek,mt8195-jpgenc-hw gghileV#cjpgenc-jpgenc@1b030000mediatek,mt8195-jpgenc-hw g{{{{e[$cjpgenc-larb@1b010000mediatek,mt8195-smi-larb  y|$$  capbsmigals-ovl@1c000000mediatek,mt8195-disp-ovle|- g .ports+port@0endpointport@1endpointrdma@1c002000mediatek,mt8195-disp-rdma e~- g . ports+port@0endpointport@1endpointcolor@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0e- .0ports+port@0endpointport@1endpointccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@e- .@ports+port@0endpointport@1endpointaal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPe- .Pports+port@0endpointport@1endpointgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`e- .`ports+port@0endpointport@1endpointdither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpe-  .pports+port@0endpointport@1endpointdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsie-*cenginedigitalhs dphyuokay+panel@0#startek,kd070fhfid078himax,hx8279  0 l SdefaultIportendpointports+port@0endpointport@1endpointdsc@1c009000mediatek,mt8195-disp-dsce- .dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi e-+cenginedigitalhs dphy udisabledmerge@1c014000mediatek,mt8195-disp-merge@e- .@dp-intf@1c015000mediatek,mt8195-dp-intfPe-,cpixelenginepll udisabledmutex@1c016000mediatek,mt8195-disp-mutex`e- .` FUlarb@1c018000mediatek,mt8195-smi-larb  y((  capbsmigals-larb@1c019000mediatek,mt8195-smi-larb  y|(  capbsmigals-~syscon@1c100000mediatek,mt8195-vdosys1syscon  .y%smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$capbsmigals0gals1-iommu@1c01f000mediatek,mt8195-iommu-vdo8 e'cbclk-mutex@1c101000mediatek,mt8195-disp-mutexe-% . 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6%dp-intf@1c113000mediatek,mt8195-dp-intf0e-%/%cpixelenginepll udisabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp .@Pph%%% %#%!%$%"%1%&%'%(%)%*cmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top- g{d{ee(6%3%4%5%6%7E=vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-txPamdp_calibration_data-e  udisableddp-tx@1c600000mediatek,mt8195-dp-tx`amdp_calibration_data-e  udisabledthermal-zonescpu0-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu1-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu2-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu3-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu4-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu5-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu6-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V cpu7-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcooling-mapsmap0 Q0 V vpu0-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalvpu1-thermal   * tripstrip-alert :L Fpassivetrip-crit : F criticalgpu-thermal   * tripstrip-alert :L Fpassivetrip-crit : F criticalgpu1-thermal   * tripstrip-alert :L Fpassivetrip-crit : F criticalvdec-thermal   * tripstrip-alert :L Fpassivetrip-crit : F criticalimg-thermal   * tripstrip-alert :L Fpassivetrip-crit : F criticalinfra-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcam0-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalcam1-thermal   *tripstrip-alert :L Fpassivetrip-crit : F criticalchosen eserial0:921600n8firmwareopteelinaro,optee-tzsmcmemory@40000000memory@reserved-memory+!optee@43200000 qC memory@50000000shared-dma-poolP q+memory@53000000shared-dma-poolS@memory@54600000 qT` memory@60000000shared-dma-pool` qmemory@62000000shared-dma-poolb@backlight-lcm0pwm-backlight x @   backlight-lcd1pwm-backlight   . x  @ udisabledcan-clk fixed-clock-1-can-clk8regulator-0regulator-fixed3edp_panel_3v3B2ZZ2Z  SdefaultIregulator-1regulator-fixed3edp_backlight_12vBZ  `SdefaultIgpio-keys gpio-keysbutton-volume-up d j 2volume_up sregulator-vio18-lcm0regulator-fixed 3vio18_lcm0  /SdefaultI regulator-vsys-lcm0regulator-fixed 3vsys_lcm0  eregulator-2regulator-fixed 3wifi_3v3B2ZZ2Z   compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7serial0ethernet0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxoutput-highdrive-strengthinput-enableinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-downoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsmemory-regionfirmware-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-0pinctrl-namesnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsmediatek,pad-selectcs-gpiosspi-max-frequencyvdd-supplyxceiver-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlesnps,reset-gpiosnps,reset-delays-usmediatek,tx-delay-psmediatek,mac-wolpinctrl-1snps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupdr_modeusb-role-switchvusb33-supplyremote-endpointbus-widthcap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapbits#phy-cellsrichtek,vinovp-microvoltLDO_VIN3-supplylabeldata-roleop-sink-microwattpower-roletry-power-rolesource-pdossink-pdospd-revisionsvidvdoirq-gpiosreset-gpiosAVDD28-supplyvcc-supplymode-switchorientation-switchmediatek,force-modeoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsbacklightenable-gpiosiovcc-supplymediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathno-mapbrightness-levelsdefault-brightness-levelnum-interpolated-stepspwmsenable-active-highdebounce-intervallinux,codevin-supplyregulator-boot-on