b8V$( U6kontron,3-5-sbc-i1200mediatek,mt8395mediatek,mt8195 +7Kontron 3.5"-SBC-i1200aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/mmc@11230000/soc/mmc@11240000/soc/serial@11001200/soc/serial@11001300/soc/serial@11001400 /soc/serial@11001500/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55'+psci9Mec3@]4p@@ cpu@100cpuarm,cortex-a55'+psci9Mec3@]4p@@ cpu@200cpuarm,cortex-a55'+psci9Mec3@]4p@@ cpu@300cpuarm,cortex-a55'+psci9Mec3@]4p@@ cpu@400cpuarm,cortex-a78'+psci9Mf]p@@ cpu@500cpuarm,cortex-a78'+psci9Mf]p@@cpu@600cpuarm,cortex-a78'+psci9Mf]p@@cpu@700cpuarm,cortex-a78'+psci9Mf]p@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state(92J_ZDcpu-retention-barm,idle-state(9-JZcpu-off-larm,idle-state(97JZHcpu-off-barm,idle-state(92JZl2-cache0cachek@wl2-cache1cachek@wl3-cachecachek @wdsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-sound disabledfixed-factor-clock-13mfixed-factor-clockclk13m(oscillator-26m fixed-clockMclk26moscillator-32k fixed-clockMclk32kperformance-controller@11bc10mediatek,cpufreq-hw ' 0 opp-table-gpuoperating-points-v2!mopp-390000000,>3 hopp-410000000,p3 opp-431000000,3 opp-473000000,1h@3 <opp-515000000,F3 <opp-556000000,!#3 Ҧopp-598000000,#3 opp-640000000,&%3 opp-670000000,'c3 opp-700000000,)'3 Lopp-730000000,+3 }opp-760000000,-L3 `opp-790000000,/q3 4opp-820000000,053 opp-850000000,23 @opp-880000000,4s3 qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.02smctimerarm,armv8-timer @   soc+ simple-busAHinterrupt-controller@c000000 arm,gic-v3Sd { '    ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8195-topckgensyscon'syscon@10001000#mediatek,mt8195-infracfg_aosyscon'syscon@10003000mediatek,mt8195-pericfgsyscon'0Apinctrl@10005000mediatek,mt8195-pinctrl'PBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint{Seth-default-pins=pins-txdMNOPpins-rxdQRSTpins-ccUVWXpins-mdioYZpins-power[\pins-reset]pins-interrupt^eth-sleep-pins>pins-txdMNOPpins-ccUXWVpins-rxdQRSTpins-mdioYZgpio-keys-pinspinsji2c0-pinsZpins "/i2c1-pins[pins  "/i2c2-default-pins\pins-bus  "/i2c3-pins]pins"/i2c4-pins^pins"/i2c6-pinsWpins"/mmc0-default-pinsCpins-clkzGfpins-cmd-dat$~}|{wvuty"epins-rstx"emmc0-uhs-pinsDpins-clkzGfpins-cmd-dat$~}|{wvuty"epins-dsGfpins-rstx"emmc1-default-pinsGpins-clkoGfpins-cmd-datnpqrs"emmc1-detect-pinsHpins-insert"nor-default-pinsUpins-ck-io Gpins-cs"pcie0-default-pinsQpins-bus "pcie1-default-pinsTpins-bus "eled-pinspins-power-enkspi0-default-pins4pins-cs-mosi-clk pins-misoGspi1-default-pins8pins-cs-mosi-clk pins-misoGuart0-pins/pins-rxc"pins-txbuart1-pins0pins-rxg"pins-txfpins-rtsdpins-ctseuart2-pins1pins-rxD"pins-txCpins-rtsBpins-ctsAuart3-pins2pins-rx"epins-txuart4-pins3pins-rx"pins-txsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd'`power-controller!mediatek,mt8195-power-controller+V+power-domain@8'+Vpower-domain@9' jmfgaltv+Vpower-domain@10' Vpower-domain@11' Vpower-domain@12' Vpower-domain@13' Vpower-domain@14'Vpower-domain@15' @AK   jvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18v+Vpower-domain@16'8$%&'()Djvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5v+Vpower-domain@17'jvppsys1vppsys1-0vppsys1-1vVpower-domain@22' $jwepsys-0wepsys-1wepsys-2wepsys-3vVpower-domain@23'jvdec0-0v+Vpower-domain@24'jvdec1-0vVpower-domain@25' jvdec2-0vVpower-domain@26'! jvenc0-larbv+Vpower-domain@27'" jvenc1-larbvVpower-domain@18' ###&jvdosys1vdosys1-0vdosys1-1vdosys1-2v+Vpower-domain@19'vVpower-domain@20'vVpower-domain@21'Qjhdmi_txVpower-domain@28'$$  jimg-0img-1v+Vpower-domain@29'Vpower-domain@30'$%jipeipe-0ipe-1vVpower-domain@31'(&&&&&jcam-0cam-1cam-2cam-3cam-4v+Vpower-domain@32' Vpower-domain@33'!Vpower-domain@34'"Vpower-domain@0'vVpower-domain@1'vVpower-domain@2'Vpower-domain@3'Vpower-domain@4'57jcsi_rx_topcsi_rx_top1Vpower-domain@5'' jetherVpower-domain@6'Xn jadspadsp1+vVpower-domain@7' g"n2jaudioaudio1audio2audio3vVwatchdog@10007000mediatek,mt8195-wdt'p.syscon@1000c000"mediatek,mt8195-apmixedsyssyscon'timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer'p (pwrap@10024000mediatek,mt8195-pwrapsyscon'@pwrap jspiwrap$pmicmediatek,mt6359{S adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5%!=Ybuck_vgpu11vgpu11 %7m= Ybuck_vmodemvmodem %m*=buck_vpuvpu %7m= Ybuck_vcorevcore % m= Ybuck_vs2vs2 5%j=Ybuck_vpavpa  %7=,buck_vproc2vproc2 %7mL= Ybuck_vproc1vproc1 %7mL= Ybuck_vcore_sshub vcore_sshub %7buck_vgpu11_sshub vgpu11_sshub %7ldo_vaud18vaud18 w@%w@=ldo_vsim1vsim1 %/M`ldo_vibrvibr O%2Zldo_vrf12vrf12 % Yldo_vusbvusb -%-=YBldo_vsram_proc2 vsram_proc2  %mL=Yldo_vio18vio18 %=Yldo_vcamiovcamio %ldo_vcn18vcn18 w@%w@=ldo_vfe28vfe28 *%*=xldo_vcn13vcn13 % ldo_vcn33_1_bt vcn33_1_bt *%5gldo_vcn33_1_wifi vcn33_1_wifi *%5gldo_vaux18vaux18 w@%w@=Yldo_vsram_others vsram_others  %m=Yldo_vefusevefuse %ldo_vxo22vxo22 w@%!Yldo_vrfckvrfck `%ldo_vrfck_1vrfck %jldo_vbif28vbif28 *%*=ldo_vio28vio28 *%2ZYldo_vemcvemc ,@ %2Zldo_vemc_1vemc &%%2ZEldo_vcn33_2_bt vcn33_2_bt *%5gldo_vcn33_2_wifi vcn33_2_wifi *%5gldo_va12va12 O% Yldo_va09va09 5%Oldo_vrf18vrf18 %Pldo_vsram_md vsram_md  %m*=Yldo_vufsvufs %Fldo_vm18vm18 %Yldo_vbbckvbbck %OYldo_vsram_proc1 vsram_proc1  %mL=Yldo_vsim2vsim2 %/M`ldo_vsram_others_sshubvsram_others_sshub  %rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi 'p pmifspmimstE(jpmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+mt6315@6mediatek,mt6315-regulator'regulatorsvbuck1Vbcpu %7=mj Ymt6315@7mediatek,mt6315-regulator'regulatorsvbuck1Vgpu h%7=mj Yninfra-iommu@10315000mediatek,mt8195-iommu-infra'1PPPNmailbox@10320000mediatek,mt8195-gce'2@mailbox@10330000mediatek,mt8195-gce'3@oscp@10500000mediatek,mt8195-scp0'Prpsramcfgl1tcmokay)mediatek/mt8195/scp.imgpclock-controller@10720000mediatek,mt8195-scp_adsp'r*dsp@10803000mediatek,mt8195-dsp '0 cfgsram,Xn*#Kjadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h+rxtx,- disabledmailbox@10816000mediatek,mt8195-adsp-mbox'`,mailbox@10817000mediatek,mt8195-adsp-mbox'p-mt8195-afe-pcm@10890000mediatek,mt8195-audio'+6. audiosysg"#neabcd2*jclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart'  jbaudbusokaydefault"/serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart'  jbaudbusokaydefault"0,serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart'  jbaudbusokaydefault"1,serial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart'  jbaudbusokaydefault"2serial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart'  jbaudbusokaydefault"3serial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart'  jbaudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc' jmainokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon'0'spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+'jparent-clksel-clkspi-clkokaydefault"4<tpm@0!infineon,slb9670tcg,tpm_tis-spi'PIthermal-sensor@1100b000mediatek,mt8195-lvts-ap' b56$nlvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svs'jmainb75(nsvs-calibration-datat-calibration-datasvs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm'+*0jmainmm disabledpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm'+Njmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+'3jparent-clksel-clkspi-clkokaydefault"8<spi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+' 4jparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+'05jparent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+'<jparent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+'=jparent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave'Rjspi disabledspi@1101e000mediatek,mt8195-spi-slave'Sjspi disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a'@macirq.jaxiapbmac_mainptp_refrmii_internalmac_cg0''RST' RST+9:; okay rgmii-id#<defaultsleep"=.>8mdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-id001c.c916' ^I'Y8 k]<stmmac-axi-configw9rx-queues-config:queue0queue1queue2queue3tx-queues-config ;queue0'queue1'queue2'queue3'usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 ' - > macippcA ?+/Bjsys_ckref_ckmcu_ck5?@: HAgokay_hostgBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci'mac,-$/B$jsys_ckref_ckmcu_ckdma_ckxhci_ckokaymmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc '#jsourcehclksource_cgokaydefaultstate_uhs"C.DuT LEFmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc '$$jsourcehclksource_cgokaydefaultstate_uhs"GH.G uT    + 9IJmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc '% Ijsourcehclksource_cg  disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu''b56$nlvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci '))> macippc5K./$''$jsys_ckref_ckmcu_ckdma_ckxhci_ck HAh:okaygB @usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 '*-*> macippcA*?+0''jsys_ckref_ckmcu_ck5L: HAiokaygBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci'mac1'jsys_ckokayusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 '+-+> macippcA+?+2'' jsys_ckref_ckmcu_ck5M: HAjokaygBusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci'mac3' jsys_ckokaypcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+'/@ pcie-mac U8A  _N i0V#&+K'/jpl_250mtl_26mtl_96mtl_32kperi_26mperi_memG5O xpcie-phy+macS ` PPPPokaydefault"Qinterrupt-controller{SPpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+'/@ pcie-mac U8A$$ $ $  _N i(WXQ'/jpl_250mtl_26mtl_96mtl_32kperi_26mperi_memH5R xpcie-phy+S ` SSSSokaydefault"Tinterrupt-controller{SSspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor'29o'' jspisfaxi+okaydefault"Uflash@0jedec,spi-nor'Pu  efuse@11c10000%mediatek,mt8195-efusemediatek,efuse'+usb3-tx-imp@184,1' dusb3-rx-imp@184,2' cusb3-intr@185' busb3-tx-imp@186,1' ausb3-rx-imp@186,2' `usb3-intr@187' _usb2-intr-p0@188,1' usb2-intr-p1@188,2' usb2-intr-p2@189,1' usb2-intr-p3@189,2' pciephy-rx-ln1@190,1' kpciephy-tx-ln1-nmos@190,2' jpciephy-tx-ln1-pmos@191,1' ipciephy-rx-ln0@191,2' hpciephy-tx-ln0-nmos@192,1' gpciephy-tx-ln0-pmos@192,2' fpciephy-glb-intr@193' edp-data@1ac'lvts1-calib@1bc'5lvts2-calib@1d0'86svs-calib@580'd7socinfo-data1@7a0't-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Aokayusb-phy@0'jref Lt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Aokayusb-phy@0'jref Mdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx' mipi_tx0_pll  disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx' mipi_tx1_pll  disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c '"V; jmaindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c '"V; jmaindma+okayM"Wdefaultpmic@34mediatek,mt6360'4{ eIRQBSregulatormediatek,mt6360-regulator X X XBUCK1 emi_vdd2 '%w@ YBUCK2 emi_vddq %  YLDO1 mt6360_ldo1 O%6LDO2 panel1_p1v8 w@%w@LDO3vmc_pmu w@%2ZJLDO5 vmch_pmu 2Z%2ZILDO6 mt6360_ldo6  % LDO7 emi_vmddr_en w@%w@Yi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ' "V; jmaindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s'0Vi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c '"Y; jmaindma+okaydefault"ZMi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c '"Y; jmaindma+okaydefault"[Mi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c ' "Y; jmaindma+okaydefault"\Mi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c '0"Y; jmaindma+okaydefault"]Mi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c '@"Y; jmaindma+okayM"^defaultclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w'PYt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+A+okayusb-phy@0'  jrefda_ref Kusb-phy@700' jrefda_ref b_`anintrrx_imptx_imp Rt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+Aokayusb-phy@0'  jrefda_ref ?usb-phy@700' jrefda_ref bbcdnintrrx_imptx_imp @phy@11e80000mediatek,mt8195-pcie-phy'sifbefghijkGnglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1+ okayOufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy' junipromp  disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm'@l0 jobmmugpu m(+ + + + + core0core1core2core3core4okay ,nclock-controller@13fbf000mediatek,mt8195-mfgcfg'lsyscon@14000000mediatek,mt8195-vppsys0syscon' 8odma-controller@14001000mediatek,mt8195-mdp3-rdma' 8o P  dp+ qq<o o ooo xdisplay@14002000mediatek,mt8195-mdp3-fg'  8o display@14003000mediatek,mt8195-mdp3-stitch'0 8o0display@14004000mediatek,mt8195-mdp3-hdr'@ 8o@"display@14005000mediatek,mt8195-mdp3-aal'PF 8oP +display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz'` 8o` P% display@14007000mediatek,mt8195-mdp3-tdshp'p 8op#display@14008000mediatek,mt8195-mdp3-color'I 8o$+display@14009000mediatek,mt8195-mdp3-ovl'J 8o%+ qqdisplay@1400a000mediatek,mt8195-mdp3-padding' 8o+display@1400b000mediatek,mt8195-mdp3-tcc' 8odma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot' 8o P + qq+ xmutex@1400f000mediatek,mt8195-vpp-mutex'P 8o+smi@14010000mediatek,mt8195-smi-sub-common'japbsmigals0 r+ssmi@14011000mediatek,mt8195-smi-sub-common'japbsmigals0 r+smi@14012000mediatek,mt8195-smi-common-vpp'  japbsmigals0gals1+rlarb@14013000mediatek,mt8195-smi-larb'0  sjapbsmi+viommu@14018000mediatek,mt8195-iommu-vpp'8 tuvwxyz{|}~Rjbclk+qclock-controller@14e00000mediatek,mt8195-wpesys'clock-controller@14e02000mediatek,mt8195-wpesys_vpp0' clock-controller@14e03000mediatek,mt8195-wpesys_vpp1'0larb@14e04000mediatek,mt8195-smi-larb'@  japbsmi+larb@14e05000mediatek,mt8195-smi-larb'P  r japbsmigals+xsyscon@14f00000mediatek,mt8195-vppsys1syscon' 8o mutex@14f01000mediatek,mt8195-vpp-mutex'{ 8o '+larb@14f02000mediatek,mt8195-smi-larb'    japbsmigals+larb@14f03000mediatek,mt8195-smi-larb'0  s japbsmigals+wdisplay@14f06000mediatek,mt8195-mdp3-split'` 8o `+,+display@14f07000mediatek,mt8195-mdp3-tcc'p 8o pdma-controller@14f08000mediatek,mt8195-mdp3-rdma' 8o  P q+ xdma-controller@14f09000mediatek,mt8195-mdp3-rdma' 8o  P  q+ xdma-controller@14f0a000mediatek,mt8195-mdp3-rdma' 8o  P  qq+ xdisplay@14f0b000mediatek,mt8195-mdp3-fg' 8o  display@14f0c000mediatek,mt8195-mdp3-fg' 8o  display@14f0d000mediatek,mt8195-mdp3-fg' 8o  display@14f0e000mediatek,mt8195-mdp3-hdr' 8o display@14f0f000mediatek,mt8195-mdp3-hdr' 8o display@14f10000mediatek,mt8195-mdp3-hdr' 8o  display@14f11000mediatek,mt8195-mdp3-aal'i 8o +display@14f12000mediatek,mt8195-mdp3-aal' j 8o +display@14f13000mediatek,mt8195-mdp3-aal'0k 8o 0!+display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz'@ 8o @ Pdisplay@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz'P 8o P P$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz'` 8o ` P%display@14f17000mediatek,mt8195-mdp3-tdshp'p 8o pdisplay@14f18000mediatek,mt8195-mdp3-tdshp' 8o (display@14f19000mediatek,mt8195-mdp3-tdshp' 8o )display@14f1a000mediatek,mt8195-mdp3-merge' 8o +display@14f1b000mediatek,mt8195-mdp3-merge' 8o +display@14f1c000mediatek,mt8195-mdp3-color't 8o +display@14f1d000mediatek,mt8195-mdp3-color' 8o u+display@14f1e000mediatek,mt8195-mdp3-color'v 8o +display@14f1f000mediatek,mt8195-mdp3-ovl'w 8o + qdisplay@14f20000mediatek,mt8195-mdp3-padding' 8o +display@14f21000mediatek,mt8195-mdp3-padding' 8o +display@14f22000mediatek,mt8195-mdp3-padding'  8o +dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot'0 8o 0 P q+ xdma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot'@ 8o @ P q+ xdma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot'P 8o P P qq+ xclock-controller@15000000mediatek,mt8195-imgsys'$larb@15001000mediatek,mt8195-smi-larb'  $$$  japbsmigals+smi@15002000mediatek,mt8195-smi-sub-common' $$japbsmigals0 r+smi@15003000mediatek,mt8195-smi-sub-common'0$$$ japbsmigals0 +clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top'larb@15120000mediatek,mt8195-smi-larb'  $japbsmi+clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr'clock-controller@15220000mediatek,mt8195-imgsys1_wpe'"larb@15230000mediatek,mt8195-smi-larb'#  $japbsmi+clock-controller@15330000mediatek,mt8195-ipesys'3%larb@15340000mediatek,mt8195-smi-larb'4  %%japbsmi+yclock-controller@16000000mediatek,mt8195-camsys'&larb@16001000mediatek,mt8195-smi-larb'  &&& japbsmigals+larb@16002000mediatek,mt8195-smi-larb'   &&japbsmi+zsmi@16004000mediatek,mt8195-smi-sub-common'@&&&japbsmigals0 +smi@16005000mediatek,mt8195-smi-sub-common'P&&japbsmigals0 r+larb@16012000mediatek,mt8195-smi-larb'   japbsmi+ {larb@16013000mediatek,mt8195-smi-larb'0  japbsmi+ larb@16014000mediatek,mt8195-smi-larb'@  japbsmi+!larb@16015000mediatek,mt8195-smi-larb'P  japbsmi+!clock-controller@1604f000mediatek,mt8195-camsys_rawa'clock-controller@1606f000mediatek,mt8195-camsys_yuva'clock-controller@1608f000mediatek,mt8195-camsys_rawb'clock-controller@160af000mediatek,mt8195-camsys_yuvb' clock-controller@16140000mediatek,mt8195-camsys_mraw'larb@16141000mediatek,mt8195-smi-larb'  && japbsmigals+"larb@16142000mediatek,mt8195-smi-larb'   japbsmi+"clock-controller@17200000mediatek,mt8195-ccusys' larb@17201000mediatek,mt8195-smi-larb'   japbsmi+|video-codec@18000000mediatek,mt8195-vcodec-dec dp q+ '@A`video-codec@2000mediatek,mtk-vcodec-lat-soc'  qqq AjselvdeclattopA+video-codec@10000mediatek,mtk-vcodec-lat'0 q AjselvdeclattopA+video-codec@25000mediatek,mtk-vcodec-core'PP q AjselvdeclattopA+larb@1800d000mediatek,mt8195-smi-larb'  japbsmi+larb@1800e000mediatek,mt8195-smi-larb'  japbsmi+clock-controller@1800f000mediatek,mt8195-vdecsys_soc'larb@1802e000mediatek,mt8195-smi-larb'  japbsmi+clock-controller@1802f000mediatek,mt8195-vdecsys'larb@1803e000mediatek,mt8195-smi-larb'   japbsmi+~clock-controller@1803f000mediatek,mt8195-vdecsys_core1' clock-controller@190f3000mediatek,mt8195-apusys_pll'0clock-controller@1a000000mediatek,mt8195-vencsys'!larb@1a010000mediatek,mt8195-smi-larb'  !!japbsmi+video-codec@1a020000mediatek,mt8195-vcodec-enc'H q`abcdvwxyU dp! jvenc_sel@++jpgdec-mastermediatek,mt8195-jpgdec+0 qmnrstu+Ajpgdec@1a040000mediatek,mt8195-jpgdec-hw'0 qmnrstuW!jjpgdec+jpgdec@1a050000mediatek,mt8195-jpgdec-hw'0 qmnrstuX!jjpgdec+jpgdec@1b040000mediatek,mt8195-jpgdec-hw'0 qqqqqqq\"jjpgdec+clock-controller@1b000000mediatek,mt8195-vencsys_core1'"syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon'  8jpgenc-mastermediatek,mt8195-jpgenc+ qqqqq+Ajpgenc@1a030000mediatek,mt8195-jpgenc-hw' qghilV!jjpgenc+jpgenc@1b030000mediatek,mt8195-jpgenc-hw' qqqqq["jjpgenc+larb@1b010000mediatek,mt8195-smi-larb'  r""  japbsmigals+}ovl@1c000000mediatek,mt8195-disp-ovl'|+ q 8ports+port@0'endpointport@1'endpoint rdma@1c002000mediatek,mt8195-disp-rdma' ~+ q 8 ports+port@0'endpoint port@1'endpoint color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color'0+ 80ports+port@0'endpoint port@1'endpoint ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr'@+ 8@ports+port@0'endpoint port@1'endpoint aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal'P+ 8Pports+port@0'endpoint port@1'endpoint gamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma'`+ 8`ports+port@0'endpoint port@1'endpoint dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither'p+  8pports+port@0'endpoint port@1'endpointdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi'+*jenginedigitalhs5 xdphy disableddsc@1c009000mediatek,mt8195-disp-dsc'+ 8dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi' ++jenginedigitalhs5 xdphy disabledmerge@1c014000mediatek,mt8195-disp-merge'@+ 8@dp-intf@1c015000mediatek,mt8195-dp-intf'P+,jpixelenginepll disabledmutex@1c016000mediatek,mt8195-disp-mutex'`+ 8` PUlarb@1c018000mediatek,mt8195-smi-larb'  ((  japbsmigals+larb@1c019000mediatek,mt8195-smi-larb'  r(  japbsmigals+tsyscon@1c100000mediatek,mt8195-vdosys1syscon'  8#smi@1c01b000mediatek,mt8195-smi-common-vdo' %&)$japbsmigals0gals1+iommu@1c01f000mediatek,mt8195-iommu-vdo'8 'jbclk+mutex@1c101000mediatek,mt8195-disp-mutex'+# 8 Plarb@1c102000mediatek,mt8195-smi-larb'   ### japbsmigals+larb@1c103000mediatek,mt8195-smi-larb'0  r##  japbsmigals+udma-controller@1c104000mediatek,mt8195-vdo1-rdma'@#+ q@ 8@ xdma-controller@1c105000mediatek,mt8195-vdo1-rdma'P#+ qq` 8P xdma-controller@1c106000mediatek,mt8195-vdo1-rdma'`#+ qA 8` xdma-controller@1c107000mediatek,mt8195-vdo1-rdma'p#+ qqa 8p xdma-controller@1c108000mediatek,mt8195-vdo1-rdma'#+ qB 8 xdma-controller@1c109000mediatek,mt8195-vdo1-rdma'#+ qqb 8 xdma-controller@1c10a000mediatek,mt8195-vdo1-rdma'#+ qC 8 xdma-controller@1c10b000mediatek,mt8195-vdo1-rdma'#+ qqc 8 xvpp-merge@1c10c000mediatek,mt8195-disp-merge'# #jmergemerge_async+ 8 #vpp-merge@1c10d000mediatek,mt8195-disp-merge'# #jmergemerge_async+ 8 #vpp-merge@1c10e000mediatek,mt8195-disp-merge'# #jmergemerge_async+ 8 #vpp-merge@1c10f000mediatek,mt8195-disp-merge'# #jmergemerge_async+ 8 #vpp-merge@1c110000mediatek,mt8195-disp-merge'# #jmergemerge_async+ 8 #dp-intf@1c113000mediatek,mt8195-dp-intf'0+#/#jpixelenginepll disabledhdr-engine@1c114000mediatek,mt8195-disp-ethdrp'@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp 8@Pph#%# ###!#$#"#1#&#'#(#)#*jmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top+ qqdqe(#3#4#5#6#7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx'Pbndp_calibration_data+  disableddp-tx@1c600000mediatek,mt8195-dp-tx'`bndp_calibration_data+  disabledthermal-zonescpu0-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu1-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu2-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu3-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu4-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu5-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu6-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L cpu7-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcooling-mapsmap0 G0 L vpu0-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalvpu1-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalgpu-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalgpu1-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalvdec-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalimg-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalinfra-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcam0-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcam1-thermal   tripstrip-alert 0L <"passivetrip-crit 0 < "criticalcpu-thermal   tripstrip-alert 0L <"passivetrip-crit 0s < "criticalpcb-top-thermal   tripstrip-alert 0$ <"passivetrip-crit 0L < "criticalpcb-bottom-thermal   tripstrip-alert 0$ <"passivetrip-crit 0L < "criticalchosen [serial0:115200n8firmwareopteelinaro,optee-tz2smcgpio-keys gpio-keysdefault"key-0 qj gvolume_up ms: xleds gpio-ledsdefault"led-0 qk keep power memory@40000000memory'@regulator-vsysregulator-fixedvsysY  LK@%LK@Xreserved-memory+Aoptee@43200000 'C memory@50000000shared-dma-pool'P )memory@53000000shared-dma-pool'S@memory@54600000 'T` memory@60000000shared-dma-pool'` memory@62000000shared-dma-pool'b@thermal-sensor-0generic-adc-thermal  sensor-channel X^hnxj'{:N aou0/@Pu`aQpD$980L)_#s(8H  X "6hIthermal-sensor-1generic-adc-thermal  sensor-channel X^hnxj'{:N aou0/@Pu`aQpD$980L)_#s(8H  X "6hIthermal-sensor-2generic-adc-thermal  sensor-channel X^hnxj'{:N aou0/@Pu`aQpD$980L)_#s(8H  X "6hI compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7mmc0mmc1serial0serial1serial2serial3serial4device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platform#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxdrive-strengthinput-enableoutput-highinput-disablebias-disablebias-pull-updrive-strength-microampbias-pull-down#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parents#sound-dai-cellsinterrupts-extended#io-channel-cellsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellsmemory-regionfirmware-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0uart-has-rtsctsmediatek,pad-selectspi-max-frequencynvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlepinctrl-1mediatek,mac-wolreset-assert-usreset-deassert-usreset-gpiossnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplybus-widthhs400-ds-delaycap-mmc-highspeedcap-mmc-hw-resetmmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplycd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcmediatek,u3p-dis-mskbus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsLDO_VIN1-supplyLDO_VIN2-supplyLDO_VIN3-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicestdout-pathlabellinux,codedebounce-intervaldefault-statefunctioncolorregulator-boot-onno-mapio-channelsio-channel-namestemperature-lookup-table