>8;(:Orenesas,smarc2-evkrenesas,rzg3e-smarcmrenesas,r9a09g047e57renesas,r9a09g047 2&Renesas SMARC EVK version 2 based on r9a09g047e57audio-clk fixed-clock,9lIopp-table-0operating-points-v2Iopp-1700000000QeSX fopp-850000000Q2X 5fopp-425000000QT@X 5fopp-212500000Q ~ X 5fwcpus cpu@0arm,cortex-a55cpupsci cpu@100arm,cortex-a55cpupsci cpu@200arm,cortex-a55cpupsci cpu@300arm,cortex-a55cpupsci cache-controller-0cacheIopp-table-1operating-points-v2Iopp-630000000Q% X 5opp-315000000QƄX 5opp-157500000Q cB`X 5opp-78750000Q0X 5opp-19687500Q,hLX 5psciarm,psci-1.0arm,psci-0.2smcqextal-clk fixed-clock,9n6I rtxin-clk fixed-clock,9Isoc simple-bus interrupt-controller@10400000renesas,r9a09g047-icu@  0       ;nmiport_irq0port_irq1port_irq2port_irq3port_irq4port_irq5port_irq6port_irq7port_irq8port_irq9port_irq10port_irq11port_irq12port_irq13port_irq14port_irq15tint0tint1tint2tint3tint4tint5tint6tint7tint8tint9tint10tint11tint12tint13tint14tint15tint16tint17tint18tint19tint20tint21tint22tint23tint24tint25tint26tint27tint28tint29tint30tint31int-ca55-0int-ca55-1int-ca55-2int-ca55-3icu-error-ca55gpt-u0-gtciadagpt-u0-gtciadbgpt-u1-gtciadagpt-u1-gtciadb KY6Ipinctrl@10410000renesas,r9a09g047-pinctrlA `p| KYIi2cI rtc-irqPS1Isd0-emmcIsd0-ctrlSD0CLKSD0CMDsd0-data@SD0DAT0SD0DAT1SD0DAT2SD0DAT3SD0DAT4SD0DAT5SD0DAT6SD0DAT7sd0-rstSD0RSTNsd0-usdsd0-cd(sd0-ctrlSD0CLKSD0CMDsd0-data SD0DAT0SD0DAT1SD0DAT2SD0DAT3sd0-iovsSD0IOVSsd0-pwenSD0PWENsd2Isd2-cdsd2-ctrlsd2-datasd2-iovssd2-pwencanfdI can1can4*+scifSCIF_TXDSCIF_RXDI sd1-pwr-en-hog sd1_pwr_ensd1Isd1-cd sd1-ctrlsd1-dataclock-controller@10420000renesas,r9a09g047-cpgB  audio_extalrtxinqextal,Isystem-controller@10430000renesas,r9a09g047-sysC Y0serial@11c01400.renesas,scif-r9a09g047renesas,scif-r9a09g057l02;erirxitxibridriteitei-drirxi-edgetxi-edge fckKY okay defaultcan@12440000renesas,r9a09g047-canfdD0;g_errg_reccch0_errch0_recch0_trxch1_errch1_recch1_trxch2_errch2_recch2_trxch3_errch3_recch3_trxch4_errch4_recch4_trxch5_errch5_recch5_trx$fckram_clkcan_clk +;ĴYPrstp_nrstc_nK okay defaultchannel0  disabledchannel1 okaychannel2  disabledchannel3  disabledchannel4 okaychannel5  disabledwatchdog@14400000,renesas,r9a09g047-wdtrenesas,r9a09g057-wdt@MN pclkoscclkYvK okaywatchdog@13000000,renesas,r9a09g047-wdtrenesas,r9a09g057-wdtOP pclkoscclkYwK  disabledwatchdog@13000400,renesas,r9a09g047-wdtrenesas,r9a09g057-wdtQR pclkoscclkYxK  disabledi2c@14400400.renesas,riic-r9a09g047renesas,riic-r9a09g057@`0 ;teiritispistinakialitmoi YK   disabledi2c@14400800.renesas,riic-r9a09g047renesas,riic-r9a09g057@`0 ;teiritispistinakialitmoi YK   disabledi2c@14400c00.renesas,riic-r9a09g047renesas,riic-r9a09g057@ `0 ;teiritispistinakialitmoi YK  okay default9pmic@12renesas,raa215300o \mainrtc xindefault fi2c@14401000.renesas,riic-r9a09g047renesas,riic-r9a09g057@`0 ;teiritispistinakialitmoi YK   disabledi2c@14401400.renesas,riic-r9a09g047renesas,riic-r9a09g057@`0 ;teiritispistinakialitmoi YK   disabledi2c@14401800.renesas,riic-r9a09g047renesas,riic-r9a09g057@`0 ;teiritispistinakialitmoi YK   disabledi2c@14401c00.renesas,riic-r9a09g047renesas,riic-r9a09g057@`0 ;teiritispistinakialitmoi YK   disabledi2c@14402000.renesas,riic-r9a09g047renesas,riic-r9a09g057@ `0  ;teiritispistinakialitmoi YK   disabledi2c@11c01000.renesas,riic-r9a09g047renesas,riic-r9a09g057`0   ;teiritispistinakialitmoi YK   disabledgpu@14850000(renesas,r9a09g047-maliarm,mali-bifrost00tusv;jobmmugpuevent$gpubusbus_aceKYPrstaxi_rstace_rst okayzinterrupt-controller@14900000 arm,gic-v3    0 Immc@15c00000.renesas,sdhi-r9a09g047renesas,sdhi-r9a09g05700coreclkhcdaclkYK okaydefaultstate_uhsvqmmc-regulator SDHI0-VQMMCw@2Z  disabledmmc@15c10000.renesas,sdhi-r9a09g047renesas,sdhi-r9a09g05700coreclkhcdaclkYK okay&3defaultstate_uhsvqmmc-regulator SDHI1-VQMMCw@2Z  disabledmmc@15c20000.renesas,sdhi-r9a09g047renesas,sdhi-r9a09g05700coreclkhcdaclkYK okaydefaultstate_uhs&3vqmmc-regulator SDHI2-VQMMCw@2Z okayItimerarm,armv8-timerPf    %;sec-physphysvirthyp-physhyp-virtaliasesA/soc/i2c@14400c00F/soc/mmc@15c00000K/soc/mmc@15c20000P/soc/serial@11c01400X/soc/mmc@15c10000memory@48000000memoryHregulator-1p8vregulator-fixed fixed-1.8Vw@w@]oIregulator-3p3vregulator-fixed fixed-3.3V2Z2Z]oIregulator-vdd0p8v-othersregulator-fixed fixed-0.8V 5 5]oIx3-clock fixed-clock,9I chosenignore_loglevelserial3:115200n8can-phy0 ti,tcan1042z  disabledcan-phy1 ti,tcan1042z  disabledregulator-vqmmc-sd1-pvddregulator-gpio SD1_PVDDw@2Z  2Zw@I compatible#address-cells#size-cellsmodel#clock-cellsclock-frequencyphandleopp-hzopp-microvoltclock-latency-nsopp-suspendregdevice_typenext-level-cacheenable-methodclocksoperating-points-v2cache-unifiedcache-sizecache-levelinterrupt-parentranges#interrupt-cellsinterrupt-controllerinterruptsinterrupt-namespower-domainsresetsgpio-controller#gpio-cellsgpio-rangespinmuxpinsbias-pull-uprenesas,output-impedancegpio-hoggpiosoutput-highline-nameclock-names#reset-cells#power-domain-cellsstatuspinctrl-0pinctrl-namesassigned-clocksassigned-clock-ratesreset-namesreg-namesinterrupts-extendedmali-supplypinctrl-1vmmc-supplyvqmmc-supplybus-widthmmc-hs200-1_8vnon-removablefixed-emmc-driver-typeregulator-nameregulator-min-microvoltregulator-max-microvoltsd-uhs-sdr50sd-uhs-sdr104i2c2mmc0mmc2serial3mmc1regulator-boot-onregulator-always-onbootargsstdout-path#phy-cellsmax-bitrategpios-states