sn8l(l#geniatech,xpi-3128rockchip,rk3128 +7Geniatech XPI-3128aliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/ethernet@2008c000/mmc@1021c000/mmc@10214000arm-pmuarm,cortex-a7-pmu0LMNOcpus+rockchip,rk3036-smpcpu@f00cpuarm,cortex-a7 cpu@f01cpuarm,cortex-a7 cpu@f02cpuarm,cortex-a7 cpu@f03cpuarm,cortex-a7 opp-table-0operating-points-v2 opp-216000000  '~~75@opp-408000000 Q '~~75@opp-600000000 #F '~~75@opp-696000000 )| '75@opp-816000000 0, 'g8g87F5@opp-1008000000 < 'OO75@opp-1200000000 G '7775@display-subsystemrockchip,display-subsystemR Xokayopp-table-1operating-points-v2 opp-200000000  'opp-300000000  'opp-400000000 ׄ '00opp-480000000 8 'timerarm,armv7-timer0   _n6oscillator fixed-clockn6xin24m 1sram@10080000 mmio-sram +  smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3128-maliarm,mali-400 Hgpgpmmupp0ppmmu0pp1ppmmu1 buscore x Xokay syscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd power-controller!rockchip,rk3128-power-controller+ power-domain@1Erz power-domain@2(power-domain@3video-codec@10106000(rockchip,rk3128-vpurockchip,rk3066-vpu` vepuvdpu (aclk_vdpuhclk_vdpuaclk_vepuhclk_vepu  iommu@10106800rockchip,iommuh C aclkiface  vop@1010e000rockchip,rk3126-vop aclk_vopdclk_vophclk_vopdef axiahbdclk Xokayport+ endpoint@0+ 6endpoint@1+ dsi@10110000*rockchip,rk3128-mipi-dsisnps,dw-mipi-dsi@ !Epclk;@dphy apbJ Xdisabledports+port@0endpoint+ port@1qos@1012d000rockchip,rk3128-qossyscon  qos@1012e000rockchip,rk3128-qossyscon  qos@1012f000rockchip,rk3128-qossyscon  qos@1012f080rockchip,rk3128-qossyscon  qos@1012f100rockchip,rk3128-qossyscon  qos@1012f180rockchip,rk3128-qossyscon  qos@1012f200rockchip,rk3128-qossyscon  interrupt-controller@10139000arm,cortex-a7-gic     Wl usb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2 otg}otg@ ; @usb2-phyXokayusb@101c0000 generic-ehci ;@usbXokayusb@101e0000 generic-ohci ;@usb Xdisabledi2s@10200000(rockchip,rk3128-i2srockchip,rk3066-i2s  DPi2s_clki2s_hclktxrx Xdisabledspdif@10204000,rockchip,rk3128-spdifrockchip,rk3066-spdif @ 7S mclkhclk txdefault Xdisabledspi@1020c000 rockchip,sfc  2clk_sfchclk_sfc Xdisabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@@  Drvbiuciuciu-driveciu-sample rx-tx рQresetXokay", default!"#$8CT[mmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Eswbiuciuciu-driveciu-sample rx-tx рRreset Xdisabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Guybiuciuciu-driveciu-sample rx-tx рSresetXokay",default %&'cu[i2s@10220000(rockchip,rk3128-i2srockchip,rk3066-i2s" Qi2s_clki2s_hclktxrxdefault( Xdisablednand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfcP@ Cahbnfcdefault )*+,-./0 Xdisabledclock-controller@20000000rockchip,rk3128-cru 1xin24mJ#g syscon@20008000&rockchip,rk3128-grfsysconsimple-mfd + usb2phy@17crockchip,rk3128-usb2phy| phyclk usb480m_phy2Xokay 2host-port 5 linestateXokay otg-port$#34otg-bvalidotg-idlinestateXokay hdmi@20034000rockchip,rk3128-inno-hdmi @@ -G pclkrefdefault 345 Xokayports+port@0endpoint+6 port@1endpoint+7 Rphy@20038000rockchip,rk3128-dsi-dphy @r refpclk $apb Xdisabled timer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer @  aU pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer @  aV pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer @@  ;aW pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer @`  <aX pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer @  =aY pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer @  >aZ pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt  "? Xdisabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default8 Xdisabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default9Xokay ^pwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm  ^default:Xokay _pwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm 0^default; Xdisabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c ` i2cMdefault<+ Xdisabledi2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cNdefault=+ Xdisabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cOdefault>+ Xdisabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart  n6MUbaudclkapb_pclktxrxdefault ?@A Xdisabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart @ n6NVbaudclkapb_pclktxrxdefaultBXokayserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart  n6OWbaudclkapb_pclktxrxdefaultC Xdisabledsaradc@2006c000rockchip,saradc  [>saradcapb_pclkW saradc-apbXokay+ Qi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c   i2cLdefaultD+ Xdisabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi @ ARspiclkapb_pclk txrxdefaultEFGHI+ Xdisableddma-controller@20078000arm,pl330arm,primecell @7R apb_pclki ethernet@2008c000rockchip,rk3128-gmac @89macirqeth_wake_irq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmacethJtXokayoutputJrmiiK|defaultLmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22d  MdefaultN Kpinctrlrockchip,rk3128-pinctrlJ+gpio@2007c000rockchip,gpio-bank  $@WlHEADER_5HEADER_3HEADER_22HEADER_23HEADER_19HEADER_26HEADER_21HEADER_24HEADER_18HEADER_36HEADER_13 Wgpio@20080000rockchip,gpio-bank  %AWlpHEADER_7HEADER_35HEADER_33HEADER_37HEADER_40HEADER_38HEADER_11HEADER_29HEADER_31 [gpio@20084000rockchip,gpio-bank @ &BWl:HEADER_27HEADER_8HEADER_10 Mgpio@20088000rockchip,gpio-bank  'CWl;HEADER_32HEADER_12HEADER_15 Spcfg-pull-default  Ppcfg-pull-none6 Oemmcemmc-clkCO %emmc-cmdCP &emmc-cmd1CPemmc-pwrCPemmc-bus1CPemmc-bus4@CPPPPemmc-bus8CPPPPPPPP 'gmacrgmii-pinsCP P P P PPPPPPPPPPPrmii-pinsCP P PPPPPPPP Lhdmihdmii2c-xfer COO 3hdmi-hpdCO 4hdmi-cecCO 5i2c0i2c0-xfer COO Di2c1i2c1-xfer COO <i2c2i2c2-xfer COO =i2c3i2c3-xfer COO >i2si2s-bus`CO O O O OO (i2s1-bus`COOOOOOlcdclcdc-dclkCOlcdc-denC Olcdc-hsyncC Olcdc-vsyncC Olcdc-rgb24C O OOOOOOOOOOOOOnfcflash-aleCO )flash-cleCO +flash-wrnCO 0flash-rdnCO .flash-rdyCO /flash-cs0CO ,flash-dqsCO -flash-bus8COOOOOOOO *pwm0pwm0-pinCO 8pwm1pwm1-pinCO 9pwm2pwm2-pinCO :pwm3pwm3-pinCO ;sdiosdio-clkCOsdio-cmdCPsdio-pwrenCPsdio-bus4@CPPPPsdmmcsdmmc-clkCO "sdmmc-cmdCP #sdmmc-detCP $sdmmc-wpCPsdmmc-pwrenCP \sdmmc-bus4@CPPPP !sfcsfc-bus2 CPPsfc-bus4@CPPPPsfc-clkCOsfc-cs0CPsfc-cs1CPspdifspdif-txCO spi0spi0-clkCP Gspi0-cs0C P Hspi0-txC P Espi0-rxC P Fspi0-cs1C P Ispi1-clkCPspi1-cs0CPspi1-txCPspi1-rxCPspi1-cs1CPspi2-clkC Pspi2-cs0CPspi2-txC Pspi2-rxC Puart0uart0-xfer CPO ?uart0-ctsCO @uart0-rtsCO Auart1uart1-xfer C P P Buart1-ctsCOuart1-rtsC Ouart2uart2-xfer CPO Cuart2-ctsCOuart2-rtsCOdp83848cdp83848c-rstCO Nir-receiverir-intCO Vledspower-ledCO Xspd-ledC O Yusb2host-drvCO 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compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2ethernet0mmc0mmc1interruptsinterrupt-affinityenable-methoddevice_typeregclocksresetsoperating-points-v2#cooling-cellscpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domainsmali-supply#power-domain-cellspm_qosiommus#iommu-cellsreset-namesremote-endpointphysphy-namesrockchip,grfinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizevusb_a-supplyvusb_d-supplydmasdma-names#sound-dai-cellspinctrl-namespinctrl-0fifo-depthmax-frequencybus-widthvmmc-supplydisable-wpcap-sd-highspeedno-mmcno-sdiocap-mmc-highspeedmmc-ddr-3_3vno-sdrockchip,playback-channels#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsvref-supplyarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthclock_in_outphy-supplyphy-modephy-handlemax-speedreset-assert-usreset-deassert-usreset-gpiosgpio-controller#gpio-cellsgpio-line-namesbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-ongpiostartup-delay-usvin-supplyenable-active-highfunctioncolordefault-statepwmspwm-supplypwm-dutycycle-rangeregulator-ramp-delay