e8_(1_`$,rockchip,rk3229-evbrockchip,rk3229!7Rockchip RK3229 Evaluation boardaliases=/pinctrl/gpio@11110000C/pinctrl/gpio@11120000I/pinctrl/gpio@11130000O/pinctrl/gpio@11140000U/serial@11010000]/serial@11020000e/serial@11030000m/spi@11090000r/mmc@30020000cpuscpu@f00wcpu,arm,cortex-a7pscicpu@f01wcpu,arm,cortex-a7pscicpu@f02wcpu,arm,cortex-a7pscicpu@f03wcpu,arm,cortex-a7psciopp-table-0,operating-points-v2opp-408000000Q~@ opp-600000000#Fopp-8160000000,B@opp-1008000000<opp-1200000000Gtxopp-1296000000M?d7opp-1392000000R<opp-1464000000WB\arm-pmu,arm,cortex-a7-pmu0LMNO!psci,arm,psci-1.0arm,psci-0.2smctimer,arm,armv7-timer40   Xn6oscillator ,fixed-clockXn6hxin24m{+display-subsystem,rockchip,display-subsystem i2s1@100b0000(,rockchip,rk3228-i2srockchip,rk3066-i2s @ i2s_clki2s_hclkQ  txrxdefault  disabledi2s0@100c0000(,rockchip,rk3228-i2srockchip,rk3066-i2s @ i2s_clki2s_hclkP txrx disabledspdif@100d0000,rockchip,rk3228-spdif  S mclkhclk txdefault  disabledi2s2@100e0000(,rockchip,rk3228-i2srockchip,rk3066-i2s@ i2s_clki2s_hclkR txrx disabledsyscon@11000000&,rockchip,rk3228-grfsysconsimple-mfd,io-domains",rockchip,rk3228-io-voltage-domainokay  power-controller!,rockchip,rk3228-power-controller2power-domain@48power-domain@5power-domain@6power-domain@7 power-domain@8usb2phy@760,rockchip,rk3228-usb2phy` phyclk husb480m_phy0{okayFotg-port$;<= otg-bvalidotg-idlinestateokayEhost-port >  linestateokay(Gusb2phy@800,rockchip,rk3228-usb2phy phyclk husb480m_phy1{okayHotg-port D  linestateokay(Ihost-port E  linestateokay(Jserial@11010000,snps,dw-apb-uart 7Xn6MUbaudclkapb_pclkdefault 3= disabledserial@11020000,snps,dw-apb-uart 8Xn6NVbaudclkapb_pclkdefault3= disabledserial@11030000,snps,dw-apb-uart 9Xn6OWbaudclkapb_pclkdefault3=okayefuse@11040000,rockchip,rk3228-efuse G pclk_efuseid@7cpu_leakage@17i2c@11050000,rockchip,rk3228-i2c $i2cLdefault disabledi2c@11060000,rockchip,rk3228-i2c %i2cMdefault disabledi2c@11070000,rockchip,rk3228-i2c &i2cNdefault  disabledi2c@11080000,rockchip,rk3228-i2c 'i2cOdefault! disabledspi@11090000,rockchip,rk3228-spi  1ARspiclkapb_pclkdefault"#$%& disabledwatchdog@110a0000 ,rockchip,rk3228-wdtsnps,dw-wdt  (b disabledpwm@110b0000,rockchip,rk3288-pwm J^default' disabledpwm@110b0010,rockchip,rk3288-pwm J^default(okayWpwm@110b0020,rockchip,rk3288-pwm J^default)okayXpwm@110b0030,rockchip,rk3288-pwm 0J^default* disabledtimer@110c0000,,rockchip,rk3228-timerrockchip,rk3288-timer  + a+ pclktimerclock-controller@110e0000,rockchip,rk3228-cru+xin24mU,{bHokb$#g0,eррxhррxhdma-controller@110f0000,arm,pl330arm,primecell@ apb_pclk thermal-zonescpu-thermald-tripscpu_alert0p~passive.cpu_alert1$~passive/cpu_crit_ ~criticalcooling-mapsmap0.0map1/0tsadc@11150000,rockchip,rk3228-tsadc :HXtsadcapb_pclkoHW tsadc-apbinitdefaultsleep0!1+05Ksokayb-hdmi-phy@12030000,rockchip,rk3228-hdmi-phym+sysclkrefoclkrefpclk{ hhdmiphy_phy disabled7gpu@20000000",rockchip,rk3228-maliarm,mali-400 H gpgpmmupp0ppmmu0pp1ppmmu1 buscorey2~ disabledvideo-codec@20020000(,rockchip,rk3228-vpurockchip,rk3399-vpu     vepuvdpu aclkhclk3y2iommu@20020800,rockchip,iommu    aclkifacey23video-codec@20030000*,rockchip,rk3228-vdecrockchip,rk3399-vdec   axiahbcabaccoreo4y2iommu@20030480,rockchip,iommu @ @  aclkifacey24vop@20050000,rockchip,rk3228-vop   aclk_vopdclk_vophclk_vopdef axiahbdclk5y2 disabledport endpoint@06;iommu@20053f00,rockchip,iommu ?   aclkifacey2 disabled5rga@20060000(,rockchip,rk3228-rgarockchip,rk3288-rga  !aclkhclksclky2kmn coreaxiahbiommu@20070800,rockchip,iommu   aclkifacey2 disabledhdmi@200a0000,rockchip,rk3228-dw-hdmi = #o7l{iahbisfrcecdefault 89:`hdmi7hdmiU, disabledportsport@0endpoint;6port@1mmc@300000000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@   Drvbiuciuciu-driveciu-sampledefault <=> disabledmmc@300100000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@   Eswbiuciuciu-driveciu-sampledefault ?@A disabledmmc@300200000,rockchip,rk3228-dw-mshcrockchip,rk3288-dw-mshc0@ X<4`<4` Guybiuciuciu-driveciu-sampledefault BCDSresetokay$usb@300400002,rockchip,rk3228-usbrockchip,rk3066-usbsnps,dwc20 otg2otg:L[@ E usb2-phyokayusb@30080000 ,generic-ehci0  FGusbokayusb@300a0000 ,generic-ohci0   FGusbokayusb@300c0000 ,generic-ehci0   HIusbokayusb@300e0000 ,generic-ohci0  HIusbokayusb@30100000 ,generic-ehci0 B HJusbokayusb@30120000 ,generic-ohci0 C HJusbokayethernet@30200000,rockchip,rk3228-gmac0   macirq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmacethU,okayo}~ K}jinput(LwrgmiidefaultM N 'B@0qos@31030080,rockchip,rk3228-qossyscon1 qos@31030100,rockchip,rk3228-qossyscon1 qos@31030180,rockchip,rk3228-qossyscon1 qos@31030200,rockchip,rk3228-qossyscon1 qos@31040000,rockchip,rk3228-qossyscon1 qos@31050000,rockchip,rk3228-qossyscon1 qos@31060000,rockchip,rk3228-qossyscon1 qos@31070000,rockchip,rk3228-qossyscon1 qos@31070080,rockchip,rk3228-qossyscon1 interrupt-controller@32010000 ,arm,gic-400 22 2@ 2`   pinctrl,rockchip,rk3228-pinctrlU,gpio@11110000,rockchip,gpio-bank 3@ gpio@11120000,rockchip,gpio-bank 4A gpio@11130000,rockchip,gpio-bank 5B Ngpio@11140000,rockchip,gpio-bank 6C Spcfg-pull-upRpcfg-pull-down#Qpcfg-pull-none2Ppcfg-pull-none-drv-12ma? Osdmmcsdmmc-clkNO<sdmmc-cmdNO=sdmmc-bus4@NOOOO>sdiosdio-clkNO?sdio-cmdNO@sdio-bus4@NOOOOAemmcemmc-clkNPBemmc-cmdNPCemmc-bus8NPPPPPPPPDgmacrgmii-pinsNP PPOOOO O OPPPP PPMrmii-pinsNP PPOO OPPPPphy-pins NPPhdmihdmi-hpdNQ9hdmii2c-xfer NPP8hdmi-cecNP:i2c0i2c0-xfer NPPi2c1i2c1-xfer NPPi2c2i2c2-xfer NPP i2c3i2c3-xfer NPP!spi0spi0-clkN R"spi0-cs0NR%spi0-txN R#spi0-rxN R$spi0-cs1N R&spi1spi1-clkNRspi1-cs0NRspi1-rxNRspi1-txNRspi1-cs1NRi2s1i2s1-busNP P P P PPPPP pwm0pwm0-pinNP'pwm1pwm1-pinNP(pwm2pwm2-pinN P)pwm3pwm3-pinN P*spdifspdif-txNP tsadcotp-pinNP0otp-outNP1uart0uart0-xfer NPPuart0-ctsNPuart0-rtsNPuart1uart1-xfer N P Puart1-ctsNPuart1-rtsN Puart2uart2-xfer NRPuart21-xfer N R Puart2-ctsNPuart2-rtsNPkeyspwr-keyNRYusbhost-vbus-drvNPTmemory@60000000wmemory`@regulator-dc-12v,regulator-fixed\dc_12vkVext_gmac ,fixed-clockXsY@ hext_gmac{Kregulator-vcc-host,regulator-fixed SdefaultT \vcc_hostkUregulator-vcc-phy,regulator-fixed\vcc_phyw@w@kLregulator-vcc-sys,regulator-fixed\vcc_syskLK@LK@VUregulator-vccio-1v8,regulator-fixed \vccio_1v8w@w@kUregulator-vccio-3v3,regulator-fixed \vccio_3v32Z2ZkU regulator-vdd-arm,pwm-regulatorWaU\vdd_arm~\kregulator-vdd-log,pwm-regulatorXaU\vdd_logB@ kgpio-keys ,gpio-keysdefaultYpower-keyGPIO Key Power Std# #address-cells#size-cellsinterrupt-parentcompatiblemodelgpio0gpio1gpio2gpio3serial0serial1serial2spi0mmc0device_typeregresetsoperating-points-v2#cooling-cellsclocksenable-methodcpu-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsportsclock-namesdmasdma-namespinctrl-namespinctrl-0statusvccio1-supplyvccio2-supplyvccio4-supply#power-domain-cellspm_qosinterrupt-names#phy-cellsphy-supplyreg-shiftreg-io-width#pwm-cellsrockchip,grf#reset-cellsassigned-clocksassigned-clock-rates#dma-cellsarm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicereset-namespinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-temprockchip,hw-tshut-modepower-domainsiommus#iommu-cellsremote-endpointassigned-clock-parentsphysphy-namesfifo-depthmax-frequencybus-widthrockchip,default-sample-phasecap-mmc-highspeednon-removabledr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeclock_in_outphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayinterrupt-controller#interrupt-cellsrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthrockchip,pinsregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplypwmspwm-supplyautorepeatlabelgpioslinux,codedebounce-intervalwakeup-source