8X( *rockchip,rk3288-evb-rk808rockchip,rk3288&7Rockchip RK3288 EVB RK808aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]dr~ cpu@501#cpuarm,cortex-a12/3:N]drcpu@502#cpuarm,cortex-a12/3:N]drcpu@503#cpuarm,cortex-a12/3:N]dropp-table-0operating-points-v2opp-126000000 @opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ]a  5pclktimerdisplay-subsystemrockchip,display-subsystemA mmc@ff0c0000rockchip,rk3288-dw-mshcGр ]Drv5biuciuciu-driveciu-sampleU / @3`resetlokays}default mmc@ff0d0000rockchip,rk3288-dw-mshcGр ]Esw5biuciuciu-driveciu-sampleU !/ @3`reset ldisabledmmc@ff0e0000rockchip,rk3288-dw-mshcGр ]Ftx5biuciuciu-driveciu-sampleU "/@3`reset ldisabledmmc@ff0f0000rockchip,rk3288-dw-mshcGр ]Guy5biuciuciu-driveciu-sampleU #/@3`resetlokays}defaultsaradc@ff100000rockchip,saradc/ $]I[5saradcapb_pclk3W `saradc-apblokay{spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi]AR5spiclkapb_pclk  txrx ,default/ ldisabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi]BS5spiclkapb_pclk txrx -default / ldisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi]CT5spiclkapb_pclktxrx .default!"#$/ ldisabledi2c@ff140000rockchip,rk3288-i2c/ >5i2c]Mdefault% ldisabledi2c@ff150000rockchip,rk3288-i2c/ ?5i2c]Odefault& ldisabledi2c@ff160000rockchip,rk3288-i2c/ @5i2c]Pdefault' ldisabledi2c@ff170000rockchip,rk3288-i2c/ A5i2c]Qdefault(lokaynserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7)3]MU5baudclkapb_pclktxrxdefault)lokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8)3]NV5baudclkapb_pclktxrxdefault*lokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9)3]OW5baudclkapb_pclkdefault+lokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :)3]PX5baudclkapb_pclktxrxdefault,lokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;)3]QY5baudclkapb_pclk  txrxdefault-lokaydma-controller@ff250000arm,pl330arm,primecell/%@@Kf] 5apb_pclkthermal-zonesreserve-thermal}.cpu-thermal}d.tripscpu_alert0p*passive/cpu_alert1$*passive0cpu_crit_ *criticalcooling-mapsmap0/0map100gpu-thermal}d.tripsgpu_alert0p*passive1gpu_crit_ *criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc/( %]HZ5tsadcapb_pclk3 `tsadc-apbinitdefaultsleep3435slokay*A.ethernet@ff290000rockchip,rk3288-gmac/)\macirqeth_wake_irq58]fgc]M5stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B `stmmacethlokayl6wrgmiiinput 7 'B@8default90usb@ff500000 generic-ehci/P ]:usblokayusb@ff520000 generic-ohci/R )]:usb ldisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T ]5otghost; usb2-phylokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X ]5otgotg/AP@@ < usb2-phy ldisabledusb@ff5c0000 generic-ehci/\ ] ldisableddma-controller@ff600000arm,pl330arm,primecell/`@@Kf] 5apb_pclk ldisabledi2c@ff650000rockchip,rk3288-i2c/e <5i2c]Ldefault=lokaypmic@1brockchip,rk808/&>default?@_xin32krk808-clkout2AAAAAABBABCregulatorsDCDC_REG1"6H q`pxvdd_arm regulator-state-memDCDC_REG2"6H P`xvdd_gpusregulator-state-memB@DCDC_REG3"6xvcc_ddrregulator-state-memDCDC_REG4"6H2Z`2Zxvcc_ioBregulator-state-mem2ZLDO_REG1"6H2Z`2Z xvccio_pmuCregulator-state-mem2ZLDO_REG2"6H2Z`2Zxvcc_tpregulator-state-memLDO_REG3"6HB@`B@xvdd_10regulator-state-memB@LDO_REG4"6Hw@`w@ xvcc18_lcdregulator-state-memw@LDO_REG5"6Hw@`2Z xvccio_sdregulator-state-mem2ZLDO_REG6"6HB@`B@ xvdd10_lcdregulator-state-memB@LDO_REG7"6Hw@`w@xvcc_18regulator-state-memw@LDO_REG8"6H2Z`2Z xvcca_codecregulator-state-mem2ZSWITCH_REG1"6xvcc_wlregulator-state-memSWITCH_REG2"6xvcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2c/f =5i2c]NdefaultD ldisabledpwm@ff680000rockchip,rk3288-pwm/hdefaultE]_lokay~pwm@ff680010rockchip,rk3288-pwm/hdefaultF]_ ldisabledpwm@ff680020rockchip,rk3288-pwm/h defaultG]_ ldisabledpwm@ff680030rockchip,rk3288-pwm/h0defaultH]_ ldisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerh Zpower-domain@9/ ]chgfdehilkj$IJKLMNOPQpower-domain@11/ ]opRSpower-domain@12/ ]Tpower-domain@13/ ]UVreboot-modesyscon-reboot-modeRB RBRB +RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/v] 5xin24m57Hjk$D#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w5edp-phyrockchip,rk3288-dp-phy]h524mYlokayjio-domains"rockchip,rk3288-io-voltage-domain ldisabledusbphyrockchip,rk3288-usb-phylokayusb-phy@320Y/ ]]5phyclk3 `phy-reset<usb-phy@334Y/4]^5phyclk3 `phy-reset:usb-phy@348Y/H]_5phyclk3 `phy-reset;watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/]p Olokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/d]T 5mclkhclkWtx 6defaultX5 ldisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/d 5]R5i2s_clki2s_hclkWWtxrxdefaultYu ldisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 ]}5aclkhclksclkapb_pclk3 `crypto-rstiommu@ff900800rockchip,iommu/@ ] 5aclkiface ldisablediommu@ff914000rockchip,iommu /@P ] 5aclkiface ldisabledrga@ff920000rockchip,rk3288-rga/ ]j5aclkhclksclkZ 3ilm `coreaxiahbvop@ff930000rockchip,rk3288-vop / ]5aclk_vopdclk_vophclk_vopZ 3def `axiahbdclk[lokayport endpoint@0/\oendpoint@1/]kendpoint@2/^eendpoint@3/_hiommu@ff930300rockchip,iommu/ ] 5aclkifaceZ lokay[vop@ff940000rockchip,rk3288-vop / ]5aclk_vopdclk_vophclk_vopZ 3 `axiahbdclk`lokayport endpoint@0/apendpoint@1/blendpoint@2/cfendpoint@3/diiommu@ff940300rockchip,iommu/ ] 5aclkifaceZ lokay`dsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ ]~d 5refpclkZ 5 ldisabledportsport@0/endpoint@0/e^endpoint@1/fcport@1/lvds@ff96c000rockchip,rk3288-lvds/@]g 5pclk_lvdslcdcgZ 5 ldisabledportsport@0/endpoint@0/h_endpoint@1/idport@1/dp@ff970000rockchip,rk3288-dp/@ b]ic5dppclkjdpZ 3o`dp5lokayportsport@0/endpoint@0/k]endpoint@1/lbport@1/endpoint@0/mhdmi@ff980000rockchip,rk3288-dw-hdmi/3 g]hmn5iahbisfrcecZ 5dlokaynportsport@0/endpoint@0/o\endpoint@1/paport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   \vepuvdpu] 5aclkhclkqZ iommu@ff9a0800rockchip,iommu/ ] 5aclkifaceZ qiommu@ff9c0440rockchip,iommu /@@@ o] 5aclkiface ldisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ \jobmmugpu]:rNZ lokay s2opp-table-1operating-points-v2ropp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ Uqos@ffaa0080rockchip,rk3288-qossyscon/ Vqos@ffad0000rockchip,rk3288-qossyscon/ Jqos@ffad0100rockchip,rk3288-qossyscon/ Kqos@ffad0180rockchip,rk3288-qossyscon/ Lqos@ffad0400rockchip,rk3288-qossyscon/ Mqos@ffad0480rockchip,rk3288-qossyscon/ Nqos@ffad0500rockchip,rk3288-qossyscon/ Iqos@ffad0800rockchip,rk3288-qossyscon/ Oqos@ffad0880rockchip,rk3288-qossyscon/ Pqos@ffad0900rockchip,rk3288-qossyscon/ Qqos@ffae0000rockchip,rk3288-qossyscon/ Tqos@ffaf0000rockchip,rk3288-qossyscon/ Rqos@ffaf0080rockchip,rk3288-qossyscon/ Sdma-controller@ffb20000arm,pl330arm,primecell/@@Kf] 5apb_pclkWefuse@ffb40000rockchip,rk3288-efuse/ ]q 5pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400.@/ @ `   pinctrlrockchip,rk3288-pinctrl5gpio@ff750000rockchip,gpio-bank/u Q]@?O.>gpio@ff780000rockchip,gpio-bank/x R]A?O.gpio@ff790000rockchip,gpio-bank/y S]B?O.gpio@ff7a0000rockchip,gpio-bank/z T]C?O.gpio@ff7b0000rockchip,gpio-bank/{ U]D?O.7gpio@ff7c0000rockchip,gpio-bank/| V]E?O.gpio@ff7d0000rockchip,gpio-bank/} W]F?O.gpio@ff7e0000rockchip,gpio-bank/~ X]G?O.|gpio@ff7f0000rockchip,gpio-bank/ Y]H?O.hdmihdmi-cec-c0[thdmi-cec-c7[thdmi-ddc [tthdmi-ddc-unwedge [utpcfg-output-lowiupcfg-pull-uptvpcfg-pull-downwpcfg-pull-nonetpcfg-pull-none-12ma zsuspendglobal-pwroff[t@ddrio-pwroff[tddr0-retention[vddr1-retention[vedpedp-hpd[ wi2c0i2c0-xfer [tt=i2c1i2c1-xfer [tt%i2c2i2c2-xfer [ t tDi2c3i2c3-xfer [tt&i2c4i2c4-xfer [tt'i2c5i2c5-xfer [tt(i2s0i2s0-bus`[ttttttYlcdclcdc-ctl@[ttttgsdmmcsdmmc-clk[x sdmmc-cmd[ysdmmc-cd[vsdmmc-bus1[vsdmmc-bus4@[yyyysdmmc-pwr[ tsdio0sdio0-bus1[vsdio0-bus4@[vvvvsdio0-cmd[vsdio0-clk[tsdio0-cd[vsdio0-wp[vsdio0-pwr[vsdio0-bkpwr[vsdio0-int[vsdio1sdio1-bus1[vsdio1-bus4@[vvvvsdio1-cd[vsdio1-wp[vsdio1-bkpwr[vsdio1-int[vsdio1-cmd[vsdio1-clk[tsdio1-pwr[ vemmcemmc-clk[temmc-cmd[vemmc-pwr[ vemmc-bus1[vemmc-bus4@[vvvvemmc-bus8[vvvvvvvvspi0spi0-clk[ vspi0-cs0[ vspi0-tx[vspi0-rx[vspi0-cs1[vspi1spi1-clk[ vspi1-cs0[ v spi1-rx[vspi1-tx[vspi2spi2-cs1[vspi2-clk[v!spi2-cs0[v$spi2-rx[v#spi2-tx[ v"uart0uart0-xfer [vt)uart0-cts[vuart0-rts[tuart1uart1-xfer [v t*uart1-cts[ vuart1-rts[ tuart2uart2-xfer [vt+uart3uart3-xfer [vt,uart3-cts[ vuart3-rts[ tuart4uart4-xfer [vt-uart4-cts[ vuart4-rts[ ttsadcotp-pin[ t3otp-out[ t4pwm0pwm0-pin[tEpwm1pwm1-pin[tFpwm2pwm2-pin[tGpwm3pwm3-pin[tHgmacrgmii-pins[ttttzzzzttt zztt9rmii-pins[ttttttttttspdifspdif-tx[ tXpcfg-pull-none-drv-8maxpcfg-pull-up-drv-8matybacklightbl-en[t}buttonspwrbtn[vlcdlcd-cs[tpmicpmic-int[v?usbhost-vbus-drv[teth_phyeth-phy-pwr[tmemory@0#memory/adc-keys adc-keys{buttonsw@button-up Volume Upsbutton-down Volume Downrbutton-menuMenu button-escEscB@button-homeHomef backlightpwm-backlight   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  9|default} F~B@external-gmac-clock fixed-clocksY@ ext_gmac8panellg,lp079qx1-sp0v K 9| Uportsportendpointmgpio-keys gpio-keys bdefaultkey-power @>tGPIO Key Power m ~dregulator-vcc-hostregulator-fixed  >default xvcc_host"6regulator-vcc-phyregulator-fixed  >defaultxvcc_phyH2Z`2Z"66regulator-vsysregulator-fixedxvcc_sysHLK@`LK@"6Aregulator-sdmmcregulator-fixed | defaultxvcc_sdH2Z`2Z  B #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltbrightness-levelsdefault-brightness-levelenable-gpiospwmsbacklightpower-supplyautorepeatlinux,input-typedebounce-intervalenable-active-highstartup-delay-usvin-supply