98( p,firefly,firefly-rk3288-betarockchip,rk3288&7Firefly-RK3288 Betaaliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]dr~ cpu@501#cpuarm,cortex-a12/3:N]drcpu@502#cpuarm,cortex-a12/3:N]drcpu@503#cpuarm,cortex-a12/3:N]dropp-table-0operating-points-v2opp-126000000 @opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ]a  5pclktimerdisplay-subsystemrockchip,display-subsystemA mmc@ff0c0000rockchip,rk3288-dw-mshcGр ]Drv5biuciuciu-driveciu-sampleU / @3`resetlokays}default mmc@ff0d0000rockchip,rk3288-dw-mshcGр ]Esw5biuciuciu-driveciu-sampleU !/ @3`resetlokaysdefault mmc@ff0e0000rockchip,rk3288-dw-mshcGр ]Ftx5biuciuciu-driveciu-sampleU "/@3`reset ldisabledmmc@ff0f0000rockchip,rk3288-dw-mshcGр ]Guy5biuciuciu-driveciu-sampleU #/@3`resetlokays}defaultsaradc@ff100000rockchip,saradc/ $]I[5saradcapb_pclk3W `saradc-apblokayspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi]AR5spiclkapb_pclk  txrx ,default !"#/lokayspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi]BS5spiclkapb_pclk txrx -default$%&'/ ldisabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi]CT5spiclkapb_pclktxrx .default()*+/ ldisabledi2c@ff140000rockchip,rk3288-i2c/ >5i2c]Mdefault,lokayi2c@ff150000rockchip,rk3288-i2c/ ?5i2c]Odefault- ldisabledi2c@ff160000rockchip,rk3288-i2c/ @5i2c]Pdefault.lokayi2c@ff170000rockchip,rk3288-i2c/ A5i2c]Qdefault/lokay{serial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7)3]MU5baudclkapb_pclktxrxdefault 012lokayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8)3]NV5baudclkapb_pclktxrxdefault3lokayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9)3]OW5baudclkapb_pclkdefault4lokayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :)3]PX5baudclkapb_pclktxrxdefault5lokayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;)3]QY5baudclkapb_pclk  txrxdefault6 ldisableddma-controller@ff250000arm,pl330arm,primecell/%@@Kf] 5apb_pclkthermal-zonesreserve-thermal}7cpu-thermal}d7tripscpu_alert0p*passive8cpu_alert1$*passive9cpu_crit_ *criticalcooling-mapsmap080map190gpu-thermal}d7tripsgpu_alert0p*passive:gpu_crit_ *criticalcooling-mapsmap0: ;tsadc@ff280000rockchip,rk3288-tsadc/( %]HZ5tsadcapb_pclk3 `tsadc-apbinitdefaultsleep<=<>slokay*A7ethernet@ff290000rockchip,rk3288-gmac/)\macirqeth_wake_irq>8]fgc]M5stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac3B `stmmacethlokayl|?inputdefault@ABCDrgmii 'B@ E0usb@ff500000 generic-ehci/P ]Fusb ldisabledusb@ff520000 generic-ohci/R )]Fusb ldisabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T ]5otghostG usb2-phylokaydefaultHusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X ]5otgotg/AP@@ I usb2-phylokayusb@ff5c0000 generic-ehci/\ ] ldisableddma-controller@ff600000arm,pl330arm,primecell/`@@Kf] 5apb_pclk ldisabledi2c@ff650000rockchip,rk3288-i2c/e <5i2c]LdefaultJlokaysyr827@40silergy,syr827_/@|vdd_cpu Pp,@ syr828@41silergy,syr828_/A|vdd_gpu Pprtc@51haoyu,hym8563/Qxin32k&KdefaultLact8846@5aactive-semi,act8846/ZdefaultMN5@KVamyOregulatorsREG1|vcc_ddrOOREG2|vcc_io2Z2ZREG3|vdd_logREG4|vcc_20OREG5 |vccio_sd2Z2ZREG6 |vdd10_lcdB@B@REG7|vcca_18w@w@REG8|vcca_332Z2ZcREG9|vcc_lan2Z2ZDREG10|vdd_10B@B@REG11|vcc_18w@w@REG12 |vcc18_lcdw@w@i2c@ff660000rockchip,rk3288-i2c/f =5i2c]NdefaultPlokaypwm@ff680000rockchip,rk3288-pwm/hdefaultQ]_lokaypwm@ff680010rockchip,rk3288-pwm/hdefaultR]_ ldisabledpwm@ff680020rockchip,rk3288-pwm/h defaultS]_ ldisabledpwm@ff680030rockchip,rk3288-pwm/h0defaultT]_ ldisabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/spower-controller!rockchip,rk3288-power-controllerlh| hpower-domain@9/ ]chgfdehilkj$UVWXYZ[\]power-domain@11/ ]op^_power-domain@12/ ]`power-domain@13/ ]abreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/v] 5xin24m>Hljk$#gׄeрxhрxhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w>edp-phyrockchip,rk3288-dp-phy]h524m  ldisabledxio-domains"rockchip,rk3288-io-voltage-domainlokayc",d7EDSaq}usbphyrockchip,rk3288-usb-phylokayusb-phy@320 / ]]5phyclk3 `phy-resetIusb-phy@334 /4]^5phyclk3 `phy-resetFusb-phy@348 /H]_5phyclk3 `phy-resetGwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/]p Olokaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/]T 5mclkhclketx 6defaultf> ldisabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ 5]R5i2s_clki2s_hclkeetxrxdefaultg ldisabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 ]}5aclkhclksclkapb_pclk3 `crypto-rstiommu@ff900800rockchip,iommu/@ ] 5aclkiface ldisablediommu@ff914000rockchip,iommu /@P ] 5aclkiface ldisabledrga@ff920000rockchip,rk3288-rga/ ]j5aclkhclksclkh 3ilm `coreaxiahbvop@ff930000rockchip,rk3288-vop / ]5aclk_vopdclk_vophclk_voph 3def `axiahbdclkilokayport endpoint@0/j|endpoint@1/kyendpoint@2/lsendpoint@3/mviommu@ff930300rockchip,iommu/ ] 5aclkifaceh lokayivop@ff940000rockchip,rk3288-vop / ]5aclk_vopdclk_vophclk_voph 3 `axiahbdclknlokayport endpoint@0/o}endpoint@1/pzendpoint@2/qtendpoint@3/rwiommu@ff940300rockchip,iommu/ ] 5aclkifaceh lokayndsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ ]~d 5refpclkh > ldisabledportsport@0/endpoint@0/slendpoint@1/tqport@1/lvds@ff96c000rockchip,rk3288-lvds/@]g 5pclk_lvdslcdcuh > ldisabledportsport@0/endpoint@0/vmendpoint@1/wrport@1/dp@ff970000rockchip,rk3288-dp/@ b]ic5dppclkxdph 3o`dp> ldisabledportsport@0/endpoint@0/ykendpoint@1/zpport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/3 g]hmn5iahbisfrcech >lokay*{portsport@0/endpoint@0/|jendpoint@1/}oport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   \vepuvdpu] 5aclkhclk~h iommu@ff9a0800rockchip,iommu/ ] 5aclkifaceh ~iommu@ff9c0440rockchip,iommu /@@@ o] 5aclkiface ldisabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760/$ \jobmmugpu]:Nh lokay6;opp-table-1operating-points-v2opp-100000000~opp-200000000 ~opp-300000000B@opp-400000000ׄopp-600000000#Fqos@ffaa0000rockchip,rk3288-qossyscon/ aqos@ffaa0080rockchip,rk3288-qossyscon/ bqos@ffad0000rockchip,rk3288-qossyscon/ Vqos@ffad0100rockchip,rk3288-qossyscon/ Wqos@ffad0180rockchip,rk3288-qossyscon/ Xqos@ffad0400rockchip,rk3288-qossyscon/ Yqos@ffad0480rockchip,rk3288-qossyscon/ Zqos@ffad0500rockchip,rk3288-qossyscon/ Uqos@ffad0800rockchip,rk3288-qossyscon/ [qos@ffad0880rockchip,rk3288-qossyscon/ \qos@ffad0900rockchip,rk3288-qossyscon/ ]qos@ffae0000rockchip,rk3288-qossyscon/ `qos@ffaf0000rockchip,rk3288-qossyscon/ ^qos@ffaf0080rockchip,rk3288-qossyscon/ _dma-controller@ffb20000arm,pl330arm,primecell/@@Kf] 5apb_pclkeefuse@ffb40000rockchip,rk3288-efuse/ ]q 5pclk_efusecpu-id@7/cpu_leakage@17/interrupt-controller@ffc01000 arm,gic-400BW@/ @ `   pinctrlrockchip,rk3288-pinctrl>gpio@ff750000rockchip,gpio-bank/u Q]@hxBWgpio@ff780000rockchip,gpio-bank/x R]AhxBWgpio@ff790000rockchip,gpio-bank/y S]BhxBWgpio@ff7a0000rockchip,gpio-bank/z T]ChxBWgpio@ff7b0000rockchip,gpio-bank/{ U]DhxBWEgpio@ff7c0000rockchip,gpio-bank/| V]EhxBWgpio@ff7d0000rockchip,gpio-bank/} W]FhxBWgpio@ff7e0000rockchip,gpio-bank/~ X]GhxBWKgpio@ff7f0000rockchip,gpio-bank/ Y]HhxBWhdmihdmi-cec-c0hdmi-cec-c7hdmi-ddc hdmi-ddc-unwedge pcfg-output-lowpcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-12ma suspendglobal-pwroffddrio-pwroffddr0-retentionddr1-retentionedpedp-hpd i2c0i2c0-xfer Ji2c1i2c1-xfer ,i2c2i2c2-xfer   Pi2c3i2c3-xfer -i2c4i2c4-xfer .i2c5i2c5-xfer /i2s0i2s0-bus`glcdclcdc-ctl@usdmmcsdmmc-clk sdmmc-cmdsdmmc-cdsdmmc-bus1sdmmc-bus4@sdmmc-pwr sdio0sdio0-bus1sdio0-bus4@sdio0-cmdsdio0-clksdio0-cdsdio0-wpsdio0-pwrsdio0-bkpwrsdio0-intsdio1sdio1-bus1sdio1-bus4@sdio1-cdsdio1-wpsdio1-bkpwrsdio1-intsdio1-cmdsdio1-clksdio1-pwr emmcemmc-clkemmc-cmdemmc-pwr emmc-bus1emmc-bus4@emmc-bus8spi0spi0-clk spi0-cs0  spi0-tx!spi0-rx"spi0-cs1#spi1spi1-clk $spi1-cs0 'spi1-rx&spi1-tx%spi2spi2-cs1spi2-clk(spi2-cs0+spi2-rx*spi2-tx )uart0uart0-xfer 0uart0-cts1uart0-rts2uart1uart1-xfer  3uart1-cts uart1-rts uart2uart2-xfer 4uart3uart3-xfer 5uart3-cts uart3-rts uart4uart4-xfer 6uart4-cts uart4-rts tsadcotp-pin <otp-out =pwm0pwm0-pinQpwm1pwm1-pinRpwm2pwm2-pinSpwm3pwm3-pinTgmacrgmii-pins @rmii-pinsphy-int Cphy-pmebBphy-rstAspdifspdif-tx fpcfg-output-highpcfg-pull-up-drv-12ma act8846pwr-holdNpmic-vselMdvpdvp-pwr hym8563rtc-intLkeyspwr-keyledspower-led-pinwork-led-pinusb_hosthost-vbus-drvusbhub-rstHusb_otgotg-vbus-drv irir-intmemory@0#memory/adc-keys adc-keysbuttonsw@button-recovery Recovery h )regulator-dovdd-1v8regulator-fixed |dovdd_1v8w@w@dexternal-gmac-clock fixed-clocksY@ ext_gmac?ir-receivergpio-ir-receiverdefault CKgpio-keys gpio-keyskey-power I C GPIO Power tdefaultleds gpio-ledsled-0 C firefly:blue:user Wrc-feedbackdefaultled-1 C firefly:green:power Wdefault-ondefaultregulator-vsysregulator-fixed|vcc_sysLK@LK@regulator-sdmmcregulator-fixed K default|vcc_sd2Z2Z mregulator-flashregulator-fixed |vcc_flashw@w@regulator-usbregulator-fixed|vcc_5vLK@LK@regulator-usb-hostregulator-fixed ~ default |vcc_host_5vLK@LK@regulator-usb-otgregulator-fixed ~  default |vcc_otg_5vLK@LK@regulator-vcc28-dvpregulator-fixed ~  default |vcc28_dvp** #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-active-lowsnps,reset-delays-ussnps,reset-gpiotx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizefcs,suspend-voltage-selectorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-enable-ramp-delayregulator-ramp-delayvin-supplysystem-power-controllervp1-supplyvp2-supplyvp3-supplyvp4-supplyinl1-supplyinl2-supplyinl3-supply#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsaudio-supplybb-supplydvp-supplyflash0-supplyflash1-supplygpio30-supplygpio1830-supplylcdc-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltgpioswakeup-sourcelinux,default-triggerstartup-delay-usenable-active-high