m8h( 07radxa,rockpi-n8vamrs,rk3288-vmarc-somrockchip,rk3288&7Radxa ROCK Pi N8aliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000/i2c@ff140000/i2c@ff660000/i2c@ff150000/i2c@ff160000/i2c@ff170000/mmc@ff0f0000/mmc@ff0c0000/mmc@ff0d0000/mmc@ff0e0000/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500#cpuarm,cortex-a12/3:N]dr~cpu@501#cpuarm,cortex-a12/3:N]dr~cpu@502#cpuarm,cortex-a12/3:N]dr~cpu@503#cpuarm,cortex-a12/3:N]dr~opp-table-0operating-points-v2~opp-126000000 @opp-216000000  opp-312000000 opp-408000000Q opp-600000000#F opp-696000000)|~opp-8160000000,B@opp-1008000000<opp-1200000000Gopp-1416000000TfrOopp-1512000000ZJ opp-1608000000_"preserved-memorydma-unusable@fe000000/oscillator fixed-clockn6xin24m~ timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer/  H ]a  )pclktimerdisplay-subsystemrockchip,display-subsystem5 mmc@ff0c0000rockchip,rk3288-dw-mshc;р ]Drv)biuciuciu-driveciu-sampleI / @3Treset`okaygq default mmc@ff0d0000rockchip,rk3288-dw-mshc;р ]Esw)biuciuciu-driveciu-sampleI !/ @3Treset`okaygdefault mmc@ff0e0000rockchip,rk3288-dw-mshc;р ]Ftx)biuciuciu-driveciu-sampleI "/@3Treset `disabledmmc@ff0f0000rockchip,rk3288-dw-mshc;р ]Guy)biuciuciu-driveciu-sampleI #/@3Treset`okaygqdefaultsaradc@ff100000rockchip,saradc/ $]I[)saradcapb_pclk3W Tsaradc-apb `disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi]AR)spiclkapb_pclk,  1txrx ,default/ `disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi]BS)spiclkapb_pclk, 1txrx -default !"#/ `disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi]CT)spiclkapb_pclk,1txrx .default$%&'/ `disabledi2c@ff140000rockchip,rk3288-i2c/ >)i2c]Mdefault(`okayrtc@51haoyu,hym8563/Q&)hym8563default*~i2c@ff150000rockchip,rk3288-i2c/ ?)i2c]Odefault+ `disabledi2c@ff160000rockchip,rk3288-i2c/ @)i2c]Pdefault, `disabledi2c@ff170000rockchip,rk3288-i2c/ A)i2c]Qdefault-`okay~rserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart/ 7;E]MU)baudclkapb_pclk,1txrxdefault./`okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart/ 8;E]NV)baudclkapb_pclk,1txrxdefault0 `disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart/i 9;E]OW)baudclkapb_pclkdefault1`okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart/ :;E]PX)baudclkapb_pclk,1txrxdefault2 `disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart/ ;;E]QY)baudclkapb_pclk,  1txrxdefault3 `disableddma-controller@ff250000arm,pl330arm,primecell/%@R]x] )apb_pclk~thermal-zonesreserve-thermal4cpu-thermald4tripscpu_alert0p*passive~5cpu_alert1$*passive~6cpu_crit_ *criticalcooling-mapsmap050map160gpu-thermald4tripsgpu_alert0p*passive~7gpu_crit_ *criticalcooling-mapsmap07 8tsadc@ff280000rockchip,rk3288-tsadc/( %]HZ)tsadcapb_pclk3 Ttsadc-apbinitdefaultsleep9:9;%s `disabled~4ethernet@ff290000rockchip,rk3288-gmac/)usb@ff500000 generic-ehci/P ]?usb`okayusb@ff520000 generic-ohci/R )]?usb`okayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/T ])otghost@ usb2-phy`okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2/X ])otgotg!0@@ A usb2-phy`okayusb@ff5c0000 generic-ehci/\ ] `disableddma-controller@ff600000arm,pl330arm,primecell/`@R]x] )apb_pclk `disabledi2c@ff650000rockchip,rk3288-i2c/e <)i2c]LdefaultB`okaypmic@1brockchip,rk808/&CdefaultDE?`rk808-clkout1rk808-clkout2nFzFFFFFFFregulatorsDCDC_REG1vdd_arm%7 qO\regulator-state-memgDCDC_REG2vdd_gpu%7 POpregulator-state-memgDCDC_REG3vcc_ddr%regulator-state-memDCDC_REG4vcc_io%72ZO2Z~regulator-state-mem2ZLDO_REG1vcc_tp%72ZO2Zregulator-state-memgLDO_REG2 vcca_codec%72ZO2Zregulator-state-mem2ZLDO_REG3vdd_10%7B@OB@regulator-state-memB@LDO_REG4vcc_wl%7w@Ow@~[regulator-state-memLDO_REG5 vccio_sd%7w@O2Z~ regulator-state-mem2ZLDO_REG6 vdd10_lcd%7B@OB@regulator-state-memgLDO_REG7vcc_18%7w@Ow@~Zregulator-state-memw@LDO_REG8 vcc18_lcd%7w@Ow@regulator-state-memgSWITCH_REG1vcc_sd%regulator-state-memgSWITCH_REG2vcc_lcd%regulator-state-memgi2c@ff660000rockchip,rk3288-i2c/f =)i2c]NdefaultG `disabledpwm@ff680000rockchip,rk3288-pwm/hdefaultH]_`okaypwm@ff680010rockchip,rk3288-pwm/hdefaultI]_ `disabledpwm@ff680020rockchip,rk3288-pwm/h defaultJ]_`okaypwm@ff680030rockchip,rk3288-pwm/h0defaultK]_ `disabledsram@ff700000 mmio-sram/ppsmp-sram@0rockchip,rk3066-smp-sram/sram@ff720000#rockchip,rk3288-pmu-srammmio-sram/rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd/s~power-controller!rockchip,rk3288-power-controllerhL ~_power-domain@9/ ]chgfdehilkj$LMNOPQRSTpower-domain@11/ ]opUVpower-domain@12/ ]Wpower-domain@13/ ]XYreboot-modesyscon-reboot-modeRBRBRB  RBsyscon@ff740000rockchip,rk3288-sgrfsyscon/tclock-controller@ff760000rockchip,rk3288-cru/v] )xin24m;,Hjk$9#gׄeрxhрxh~syscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd/w~;edp-phyrockchip,rk3288-dp-phy]h)24mN `disabled~oio-domains"rockchip,rk3288-io-voltage-domain`okayYcqZ [usbphyrockchip,rk3288-usb-phy`okayusb-phy@320N/ ]])phyclk3 Tphy-reset~Ausb-phy@334N/4]^)phyclk3 Tphy-reset~?usb-phy@348N/H]_)phyclk3 Tphy-reset~@watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt/]p O `disabledsound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif/]T )mclkhclk,\1tx 6default]; `disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s/ 5]R)i2s_clki2s_hclk,\\1txrxdefault^ `disabledcrypto@ff8a0000rockchip,rk3288-crypto/@ 0 ]})aclkhclksclkapb_pclk3 Tcrypto-rstiommu@ff900800rockchip,iommu/@ ] )aclkiface `disablediommu@ff914000rockchip,iommu /@P ] )aclkiface `disabledrga@ff920000rockchip,rk3288-rga/ ]j)aclkhclksclk_ 3ilm Tcoreaxiahbvop@ff930000rockchip,rk3288-vop / ])aclk_vopdclk_vophclk_vop_ 3def Taxiahbdclk%``okayport~ endpoint@0/,a~tendpoint@1/,b~pendpoint@2/,c~jendpoint@3/,d~miommu@ff930300rockchip,iommu/ ] )aclkiface_ `okay~`vop@ff940000rockchip,rk3288-vop / ])aclk_vopdclk_vophclk_vop_ 3 Taxiahbdclk%e`okayport~ endpoint@0/,f~uendpoint@1/,g~qendpoint@2/,h~kendpoint@3/,i~niommu@ff940300rockchip,iommu/ ] )aclkiface_ `okay~edsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi/@ ]~d )refpclk_ ; `disabledportsport@0/endpoint@0/,j~cendpoint@1/,k~hport@1/lvds@ff96c000rockchip,rk3288-lvds/@]g )pclk_lvdslcdcl_ ; `disabledportsport@0/endpoint@0/,m~dendpoint@1/,n~iport@1/dp@ff970000rockchip,rk3288-dp/@ b]ic)dppclkodp_ 3oTdp; `disabledportsport@0/endpoint@0/,p~bendpoint@1/,q~gport@1/hdmi@ff980000rockchip,rk3288-dw-hdmi/E g]hmn)iahbisfrcec_ ;`okay<rdefaultsportsport@0/endpoint@0/,t~aendpoint@1/,u~fport@1/video-codec@ff9a0000rockchip,rk3288-vpu/   gpio@ff7c0000rockchip,gpio-bank/| V]En~H]~)gpio@ff7d0000rockchip,gpio-bank/} W]Fn~H]gpio@ff7e0000rockchip,gpio-bank/~ X]Gn~H]gpio@ff7f0000rockchip,gpio-bank/ Y]Hn~H]hdmihdmi-cec-c0x~shdmi-cec-c7xhdmi-ddc xxhdmi-ddc-unwedge yxpcfg-output-low~ypcfg-pull-up~zpcfg-pull-down~{pcfg-pull-none~xpcfg-pull-none-12ma ~~suspendglobal-pwroffx~Eddrio-pwroffxddr0-retentionzddr1-retentionzedpedp-hpd {i2c0i2c0-xfer xx~Bi2c1i2c1-xfer xx~(i2c2i2c2-xfer  x x~Gi2c3i2c3-xfer xx~+i2c4i2c4-xfer xx~,i2c5i2c5-xfer xx~-i2s0i2s0-bus`xxxxxx~^lcdclcdc-ctl@xxxx~lsdmmcsdmmc-clk|~ sdmmc-cmd}~sdmmc-cdz~sdmmc-bus1zsdmmc-bus4@}}}}~sdio0sdio0-bus1zsdio0-bus4@zzzz~sdio0-cmdz~sdio0-clkx~sdio0-cdzsdio0-wpzsdio0-pwrzsdio0-bkpwrzsdio0-intzsdio1sdio1-bus1zsdio1-bus4@zzzzsdio1-cdzsdio1-wpzsdio1-bkpwrzsdio1-intzsdio1-cmdzsdio1-clkxsdio1-pwr zemmcemmc-clkx~emmc-cmdz~emmc-pwr z~emmc-bus1zemmc-bus4@zzzzemmc-bus8zzzzzzzz~spi0spi0-clk z~spi0-cs0 z~spi0-txz~spi0-rxz~spi0-cs1zspi1spi1-clk z~ spi1-cs0 z~#spi1-rxz~"spi1-txz~!spi2spi2-cs1zspi2-clkz~$spi2-cs0z~'spi2-rxz~&spi2-tx z~%uart0uart0-xfer zx~.uart0-ctsz~/uart0-rtsxuart1uart1-xfer z x~0uart1-cts zuart1-rts xuart2uart2-xfer zx~1uart3uart3-xfer zx~2uart3-cts zuart3-rts xuart4uart4-xfer zx~3uart4-cts zuart4-rts xtsadcotp-pin x~9otp-out x~:pwm0pwm0-pinx~Hpwm1pwm1-pinx~Ipwm2pwm2-pinx~Jpwm3pwm3-pinx~Kgmacrgmii-pinsxxxx~~~~xxx ~~xx~=rmii-pinsxxxxxxxxxxspdifspdif-tx x~]hym8563hym8563-intz~*pcfg-pull-none-drv-8ma~|pcfg-pull-up-drv-8ma~}pmicpmic-intz~Dsdio-pwrseqwifi-enable-hx~vbus_hostusb1-en-ocz~vbus_typecusb0-en-oc z~external-gmac-clock fixed-clocksY@ clkin_gmac~<sdio-pwrseqmmc-pwrseq-simple] )ext_clockdefault >~regulator-vcc12v-dcinregulator-fixed vcc12v_dcin%7O~regulator-vcc5v0-sysregulator-fixed vcc5v0_sys%7LK@OLK@~Fregulator-vbus-hostregulator-fixeddefault vbus_hostF Cregulator-vbus-typecregulator-fixeddefault vbus_typecF C regulator-vccio-flashregulator-fixed vccio_flash7w@Ow@~ #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvqmmc-supplypinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104vmmc-supply#io-channel-cellsdmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-tempinterrupt-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayassigned-clocksphy-supplysnps,reset-gpiophysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplyflash0-supplygpio1830-supplygpio30-supplysdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthreset-gpiosvin-supplyenable-active-high