Š žķĶ48æ|( øæDKgoogle,veyron-jerry-rev15google,veyron-jerry-rev14google,veyron-jerry-rev13google,veyron-jerry-rev12google,veyron-jerry-rev11google,veyron-jerry-rev10google,veyron-jerry-rev7google,veyron-jerry-rev6google,veyron-jerry-rev5google,veyron-jerry-rev4google,veyron-jerry-rev3google,veyron-jerrygoogle,veyronrockchip,rk3288& 7Google Jerryaliases=/ethernet@ff290000G/pinctrl/gpio@ff750000M/pinctrl/gpio@ff780000S/pinctrl/gpio@ff790000Y/pinctrl/gpio@ff7a0000_/pinctrl/gpio@ff7b0000e/pinctrl/gpio@ff7c0000k/pinctrl/gpio@ff7d0000q/pinctrl/gpio@ff7e0000w/pinctrl/gpio@ff7f0000}/i2c@ff650000‚/i2c@ff140000‡/i2c@ff660000Œ/i2c@ff150000‘/i2c@ff160000–/i2c@ff170000›/mmc@ff0f0000”/mmc@ff0c0000§/mmc@ff0d0000­/mmc@ff0e0000³/serial@ff180000»/serial@ff190000Ć/serial@ff690000Ė/serial@ff1b0000Ó/serial@ff1c0000Ū/spi@ff110000ą/spi@ff120000å/spi@ff130000ź/mmc@ff0f0000ļ/mmc@ff0c0000ō/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0ś—˜™šcpusrockchip,rk3066-smp&cpu@5003cpuarm,cortex-a12?CJ^mtrŽ šcpu@5013cpuarm,cortex-a12?CJ^mtršcpu@5023cpuarm,cortex-a12?CJ^mtršcpu@5033cpuarm,cortex-a12?CJ^mtršopp-table-0operating-points-v2¢šopp-126000000­‚›€“ » œ@opp-216000000­ ßę“ » opp-408000000­Q–“ » opp-600000000­#ĆF“ » opp-696000000­)|“~šopp-816000000­0£,“B@opp-1008000000­<Ü“opp-1200000000­G†Œ“Čąopp-1416000000­Tfr“O€opp-1512000000­ZJ“Šopp-1608000000­_Ų"“Ö opp-1704000000­eś“™popp-1800000000­kIŅ“\Ąreserved-memoryÓdma-unusable@fe000000?žoscillator fixed-clockŚn6źxin24mżš timerarm,armv7-timer 0ś   Śn6.timer@ff810000rockchip,rk3288-timer?’  śH ma  Epclktimerdisplay-subsystemrockchip,display-subsystemQ mmc@ff0c0000rockchip,rk3288-dw-mshcWšŃ€ mČDrvEbiuciuciu-driveciu-samplee ś ?’ @C€preset|okayƒŸ°Č Ā ĖZéö*7BdefaultPmmc@ff0d0000rockchip,rk3288-dw-mshcWšŃ€ mÉEswEbiuciuciu-driveciu-samplee ś!?’ @Cpreset|okayƒŸZg}ˆBdefault Péö*wifi@1marvell,sd8897?–‰$g           ‰$g           ‰$g           ‰$g           ‰$g           ‰$g           ‰$g           ‰$g           ‰$g            ‰$g            ‰$g            ‰$g            ‰$g            ö“š‰:ˆ$          ‰:ˆ(          ‰:ˆ,          ‰:ˆ0          ‰:ˆ4          ‰:ˆ8          ‰:ˆ<          ‰:ˆ@          °×Ŗ‰:ˆd          ‰:ˆh          ‰:ˆl          ‰:ˆp          ‰:ˆt          ‰:ˆx          ‰:ˆ|          ‰:ˆ€          ‰:ˆ„          ‰:ˆˆ        ‰:ˆŒ        <ś6‰:ˆ•        ‰:ˆ™        ‰:ˆ        ‰:ˆ”        ‰:ˆ„        mmc@ff0e0000rockchip,rk3288-dw-mshcWšŃ€ mŹFtxEbiuciuciu-driveciu-samplee ś"?’@C‚preset |disabledmmc@ff0f0000rockchip,rk3288-dw-mshcWšŃ€ mĖGuyEbiuciuciu-driveciu-samplee ś#?’@Cƒpreset|okayƒĖž7}ˆBdefault Psaradc@ff100000rockchip,saradc?’ ś$,mI[Esaradcapb_pclkCW psaradc-apb |disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spimAREspiclkapb_pclk>  Ctxrx ś,BdefaultP !"#?’|okayec@0google,cros-ec-spi?M& śBdefaultP$j-ĘĄi2c-tunnelgoogle,cros-ec-i2c-tunnel|sbs-battery@bsbs,sbs-battery? Ž¢keyboard-controllergoogle,cros-ec-keyb·Ē ŚDō;<=>?@A B CD}0Y1 d"#(  \V |})  Ž + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spimBSEspiclkapb_pclk> Ctxrx ś-BdefaultP%&'(?’ |disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spimCTEspiclkapb_pclk>Ctxrx ś.BdefaultP)*+,?’|okay flash@0jedec,spi-norjśš€?i2c@ff140000rockchip,rk3288-i2c?’ ś>Ei2cmMBdefaultP-|okayŚ€2,dtpm@20infineon,slb9645tt? Ci2c@ff150000rockchip,rk3288-i2c?’ ś?Ei2cmOBdefaultP. |disabledi2c@ff160000rockchip,rk3288-i2c?’ ś@Ei2cmPBdefaultP/0|okayŚ€2,,ts3a227e@3b ti,ts3a227e?;&1śBdefaultP2[š trackpad@15elan,ekth3000?& śf3qtrackpad@2c hid-over-i2c& ś?, f3qi2c@ff170000rockchip,rk3288-i2c?’ śAEi2cmQBdefaultP4 |disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart?’ ś7Ž˜mMUEbaudclkapb_pclk>CtxrxBdefault P567|okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart?’ ś8Ž˜mNVEbaudclkapb_pclk>CtxrxBdefaultP8|okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uart?’i ś9Ž˜mOWEbaudclkapb_pclkBdefaultP9|okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart?’ ś:Ž˜mPXEbaudclkapb_pclk>CtxrxBdefaultP: |disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart?’ ś;Ž˜mQYEbaudclkapb_pclk>  CtxrxBdefaultP; |disableddma-controller@ff250000arm,pl330arm,primecell?’%@ś„°ĖmĀ Eapb_pclkšthermal-zonesreserve-thermalāčųˆ<cpu-thermalādųˆ<tripscpu_alert0p"Š:passiveš=cpu_alert1$ų"Š:passiveš>cpu_crit† "Š :criticalcooling-mapsmap0-=02’’’’’’’’’’’’’’’’map1->02’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’gpu-thermalādųˆ<tripsgpu_alert04"Š:passiveš?gpu_crit† "Š :criticalcooling-mapsmap0-? 2@’’’’’’’’tsadc@ff280000rockchip,rk3288-tsadc?’( ś%mHZEtsadcapb_pclkCŸ ptsadc-apbBinitdefaultsleepPAABKAUkCxčH|okay¦š<ethernet@ff290000rockchip,rk3288-gmac?’)śĮmacirqeth_wake_irqkC8m—fgc˜Ä]MEstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macCB pstmmaceth |disabledusb@ff500000 generic-ehci?’P śmĀŃDÖusb|okayąusb@ff520000 generic-ohci?’R ś)mĀŃDÖusb |disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2?’T śmĆEotgöhostŃE Öusb2-phyž|okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2?’X śmĮEotgöhost,>M€€@@ ŃF Öusb2-phy|okay\zlFusb@ff5c0000 generic-ehci?’\ śmÄ |disableddma-controller@ff600000arm,pl330arm,primecell?’`@ś„°ĖmĮ Eapb_pclk |disabledi2c@ff650000rockchip,rk3288-i2c?’e ś<Ei2cmLBdefaultPG|okayŚ€2,dpmic@1brockchip,rk808?źxin32kwifibt_32kin&1śBdefault PHIJƒqż¤°¼ČŌKąģų3K+K8 š”regulatorsDCDC_REG1Bvdd_armQew q° §qš regulator-state-mem¼DCDC_REG2Bvdd_gpuQew 5Š§qšregulator-state-mem¼DCDC_REG3 Bvcc135_ddrQeregulator-state-memÕDCDC_REG4Bvcc_18Qeww@w@šregulator-state-memÕķw@LDO_REG1 Bvcc33_ioQew2Z 2Z š3regulator-state-memÕķ2Z LDO_REG3Bvdd_10QewB@B@regulator-state-memÕķB@LDO_REG7Bvdd10_lcd_pwren_hQew&% &% regulator-state-mem¼SWITCH_REG1 Bvcc33_lcdQešaregulator-state-mem¼LDO_REG6 Bvcc18_codecQeww@w@šbregulator-state-mem¼LDO_REG4 Bvccio_sdww@2Z šregulator-state-mem¼LDO_REG5 Bvcc33_sdw2Z 2Z šregulator-state-mem¼LDO_REG8 Bvcc33_ccdQew2Z 2Z regulator-state-mem¼LDO_REG2Bmic_vccQeww@w@regulator-state-mem¼i2c@ff660000rockchip,rk3288-i2c?’f ś=Ei2cmNBdefaultPL|okayچ 2, max98090@10maxim,max98090?&MśEmclkmqBdefaultPNšŸpwm@ff680000rockchip,rk3288-pwm?’h BdefaultPOm_|okayš¦pwm@ff680010rockchip,rk3288-pwm?’h BdefaultPPm_|okayš›pwm@ff680020rockchip,rk3288-pwm?’h  BdefaultPQm_ |disabledpwm@ff680030rockchip,rk3288-pwm?’h0 BdefaultPRm_ |disabledsram@ff700000 mmio-sram?’p€Ó’p€smp-sram@0rockchip,rk3066-smp-sram?sram@ff720000#rockchip,rk3288-pmu-srammmio-sram?’rpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfd?’sšpower-controller!rockchip,rk3288-power-controller \hl šfpower-domain@9? ČmŹĶČĢÅƾæŌÕÖŁŃŅchgfdehilkj$ (STUVWXYZ[ power-domain@11? mĻop (\] power-domain@12? mŠÜ (^ power-domain@13? mĄ (_` reboot-modesyscon-reboot-mode /” 6RBĆ BRBĆ PRBĆ  `RBĆsyscon@ff740000rockchip,rk3288-sgrfsyscon?’tclock-controller@ff760000rockchip,rk3288-cru?’vm Exin24mkCż lH\ŃŻjŅŽk$ y#gø€ׄĶeį£šŃ€xhĄį£šŃ€xhĄšsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfd?’wšCedp-phyrockchip,rk3288-dp-phymhE24m Ž|okayšvio-domains"rockchip,rk3288-io-voltage-domain|okay ™3 £ ® ¼3 Ģ3 Śa ę ņb ’usbphyrockchip,rk3288-usb-phy|okayusb-phy@320 Ž? m]EphyclkżC… pphy-resetšFusb-phy@334 Ž?4m^EphyclkżCˆ pphy-resetšDusb-phy@348 Ž?Hm_EphyclkżC‹ pphy-resetšEwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt?’€mp śO|okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif?’‹ mTŠ Emclkhclk>cCtx ś6BdefaultPdkC |disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s?’‰  ś5mRĪEi2s_clki2s_hclk>ccCtxrxBdefaultPe  9|okayšžcrypto@ff8a0000rockchip,rk3288-crypto?’Š@ ś0 mĒĶ}ĮEaclkhclksclkapb_pclkC® pcrypto-rstiommu@ff900800rockchip,iommu?’@ śmŹŌ Eaclkiface S |disablediommu@ff914000rockchip,iommu ?’‘@’‘P śmĶÕ Eaclkiface S ` |disabledrga@ff920000rockchip,rk3288-rga?’’€ śmČÖjEaclkhclksclk {f Cilm pcoreaxiahbvop@ff930000rockchip,rk3288-vop ?’“œ’“ śmžŃEaclk_vopdclk_vophclk_vop {f Cdef paxiahbdclk ‰g|okayportš endpoint@0? hš}endpoint@1? išxendpoint@2? jšqendpoint@3? kštiommu@ff930300rockchip,iommu?’“ śmÅŃ Eaclkiface {f  S|okayšgvop@ff940000rockchip,rk3288-vop ?’”œ’” śmĘæŅEaclk_vopdclk_vophclk_vop {f C°±² paxiahbdclk ‰l|okayportš endpoint@0? mš~endpoint@1? nšyendpoint@2? ošrendpoint@3? pšuiommu@ff940300rockchip,iommu?’” śmĘŅ Eaclkiface {f  S|okayšldsi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi?’–@ śm~d Erefpclk {f kC |disabledportsport@0?endpoint@0? qšjendpoint@1? ršoport@1?lvds@ff96c000rockchip,rk3288-lvds?’–Ą@mg Epclk_lvdsBlcdcPs {f kC |disabledportsport@0?endpoint@0? tškendpoint@1? ušpport@1?dp@ff970000rockchip,rk3288-dp?’—@ śbmicEdppclkŃvÖdp {f CopdpkC|okayBdefaultPwportsport@0?endpoint@0? xšiendpoint@1? yšnport@1?endpoint@0? zšŖhdmi@ff980000rockchip,rk3288-dw-hdmi?’˜˜ śgmhmnEiahbisfrcec {f kC |okayBdefaultunwedgeP{A|š”portsport@0?endpoint@0? }šhendpoint@1? ~šmport@1?video-codec@ff9a0000rockchip,rk3288-vpu?’šś   ĮvepuvdpumŠÜ Eaclkhclk ‰ {f iommu@ff9a0800rockchip,iommu?’š ś mŠÜ Eaclkiface S {f šiommu@ff9c0440rockchip,iommu ?’œ@@’œ€@ śomĻŪ Eaclkiface S |disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760?’£$ś ĮjobmmugpumĄJ€^ {f |okay  š@opp-table-1operating-points-v2š€opp-100000000­õį“~šopp-200000000­ ėĀ“~šopp-300000000­į£“B@opp-400000000­ׄ“Čąopp-600000000­#ĆF“Šqos@ffaa0000rockchip,rk3288-qossyscon?’Ŗ š_qos@ffaa0080rockchip,rk3288-qossyscon?’Ŗ€ š`qos@ffad0000rockchip,rk3288-qossyscon?’­ šTqos@ffad0100rockchip,rk3288-qossyscon?’­ šUqos@ffad0180rockchip,rk3288-qossyscon?’­€ šVqos@ffad0400rockchip,rk3288-qossyscon?’­ šWqos@ffad0480rockchip,rk3288-qossyscon?’­€ šXqos@ffad0500rockchip,rk3288-qossyscon?’­ šSqos@ffad0800rockchip,rk3288-qossyscon?’­ šYqos@ffad0880rockchip,rk3288-qossyscon?’­€ šZqos@ffad0900rockchip,rk3288-qossyscon?’­ š[qos@ffae0000rockchip,rk3288-qossyscon?’® š^qos@ffaf0000rockchip,rk3288-qossyscon?’Æ š\qos@ffaf0080rockchip,rk3288-qossyscon?’ƀ š]dma-controller@ffb20000arm,pl330arm,primecell?’²@ś„°ĖmĮ Eapb_pclkšcefuse@ffb40000rockchip,rk3288-efuse?’“ mq Epclk_efusecpu-id@7?cpu_leakage@17?interrupt-controller@ffc01000 arm,gic-400 ¬ Į@?’Ą’Ą ’Ą@ ’Ą`  ś špinctrlrockchip,rk3288-pinctrlkC&ÓBdefaultsleepP‚ƒ„…†A‚ƒ„‡ˆgpio@ff750000rockchip,gpio-bank?’u śQm@ Ņ ā ¬ Įē īPMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFAULT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTš1gpio@ff780000rockchip,gpio-bank?’x śRmA Ņ ā ¬ Įgpio@ff790000rockchip,gpio-bank?’y śSmB Ņ ā ¬ ĮM īCONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENš“gpio@ff7a0000rockchip,gpio-bank?’z śTmC Ņ ā ¬ Į‚ īFLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank?’{ śUmD Ņ ā ¬ Į³ īUART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEš–gpio@ff7c0000rockchip,gpio-bank?’| śVmE Ņ ā ¬ ĮA īSPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENš™gpio@ff7d0000rockchip,gpio-bank?’} śWmF Ņ ā ¬ Į© īI2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDšMgpio@ff7e0000rockchip,gpio-bank?’~ śXmG Ņ ā ¬ ĮŚ īLCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKEDP_HPDDVS1nFAULT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDš gpio@ff7f0000rockchip,gpio-bank?’ śYmH Ņ ā ¬ Į^ īRAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 ž‰hdmi-cec-c7 ž‰hdmi-ddc ž‰‰š{hdmi-ddc-unwedge žŠ‰š|vcc50-hdmi-en ž‰ššpcfg-output-low šŠpcfg-pull-up š‹pcfg-pull-down $špcfg-pull-none 3š‰pcfg-pull-none-12ma 3 @ šsuspendglobal-pwroff ž‰š„ddrio-pwroff ž‰šƒddr0-retention ž‹š‚ddr1-retention ž‹suspend-l-wake žŠš…suspend-l-sleep žŒš‡edpedp-hpd ž šwi2c0i2c0-xfer ž‰‰šGi2c1i2c1-xfer ž‰‰š-i2c2i2c2-xfer ž ‰ ‰šLi2c3i2c3-xfer ž‰‰š.i2c4i2c4-xfer ž‰‰š/i2c5i2c5-xfer ž‰‰š4i2s0i2s0-bus` ž‰‰‰‰‰‰šelcdclcdc-ctl@ ž‰‰‰‰šssdmmcsdmmc-clk žŽšsdmmc-cmd žŽšsdmmc-cd ž‹sdmmc-bus1 ž‹sdmmc-bus4@ žŽŽŽŽšsdmmc-cd-disabled ž‰šsdmmc-cd-pin ž‰šsdio0sdio0-bus1 ž‹sdio0-bus4@ žŽŽŽŽšsdio0-cmd žŽšsdio0-clk žŽšsdio0-cd ž‹sdio0-wp ž‹sdio0-pwr ž‹sdio0-bkpwr ž‹sdio0-int ž‹wifienable-h ž‰š•bt-enable-l ž‰bt-host-wake žbt-host-wake-l ž‰bt-dev-wake-sleep žŠšˆbt-dev-wake-awake žŒš†bt-dev-wake ž‰sdio1sdio1-bus1 ž‹sdio1-bus4@ ž‹‹‹‹sdio1-cd ž‹sdio1-wp ž‹sdio1-bkpwr ž‹sdio1-int ž‹sdio1-cmd ž‹sdio1-clk ž‰sdio1-pwr ž ‹emmcemmc-clk žŽšemmc-cmd žŽšemmc-pwr ž ‹emmc-bus1 ž‹emmc-bus4@ ž‹‹‹‹emmc-bus8€ žŽŽŽŽŽŽŽŽšemmc-reset ž ‰š’spi0spi0-clk ž ‹š spi0-cs0 ž ‹š#spi0-tx ž‹š!spi0-rx ž‹š"spi0-cs1 ž‹spi1spi1-clk ž ‹š%spi1-cs0 ž ‹š(spi1-rx ž‹š'spi1-tx ž‹š&spi2spi2-cs1 ž‹spi2-clk ž‹š)spi2-cs0 ž‹š,spi2-rx ž‹š+spi2-tx ž ‹š*uart0uart0-xfer ž‹‰š5uart0-cts ž‹š6uart0-rts ž‰š7uart1uart1-xfer ž‹ ‰š8uart1-cts ž ‹uart1-rts ž ‰uart2uart2-xfer ž‹‰š9uart3uart3-xfer ž‹‰š:uart3-cts ž ‹uart3-rts ž ‰uart4uart4-xfer ž‹‰š;uart4-cts ž ‹uart4-rts ž ‰tsadcotp-pin ž ‰šAotp-out ž ‰šBpwm0pwm0-pin ž‰šOpwm1pwm1-pin ž‰šPpwm2pwm2-pin ž‰šQpwm3pwm3-pin ž‰šRgmacrgmii-pinsš ž‰‰‰‰‰‰‰ ‰‰rmii-pins  ž‰‰‰‰‰‰‰‰‰‰spdifspdif-tx ž ‰šdpcfg-pull-none-drv-8ma 3 @šŽpcfg-pull-up-drv-8ma  @pcfg-output-high OšŒbuttonspwr-key-l ž‹šap-lid-int-l ž‹š¬pmicpmic-int-l ž‹šHdvs-1 ž šIdvs-2 žšJrebootap-warm-reset-h ž ‰š‘recovery-switchrec-mode-l ž ‹tpmtpm-int-h ž‰write-protectfw-wp-ap ž‰codechp-det ž‹šint-codec žšNmic-det ž ‹šœheadsetts3a227e-int-l ž‹š2backlightbl_pwr_en ž ‰š¢bl-en ž‰š„lcdlcd-en ž‰š£avdd-1v8-disp-en ž ‰š¤chargerac-present-ap ž‹š«cros-ecec-int ž‰š$trackpadtrackpad-int ž‹š0usb-hosthost1-pwr-en ž ‰š­usbotg-pwren-h ž ‰š®buck-5vdrv-5v ž‰š˜chosen [serial2:115200n8memory3memory?€power-button gpio-keysBdefaultPkey-power gPower Å1 mt xdqgpio-restart gpio-restart Å1 BdefaultP‘ ŠČemmc-pwrseqmmc-pwrseq-emmcP’Bdefault ““ šsdio-pwrseqmmc-pwrseq-simplem” Eext_clockBdefaultP• “–šregulator-vcc-5vregulator-fixedBvcc_5vQewLK@LK@ Ÿ— Ŗ ½ BdefaultP˜šKregulator-vcc33-sysregulator-fixed Bvcc33_sysQew2Z 2Z  Ÿ—šregulator-vcc50-hdmiregulator-fixed Bvcc50_hdmiQe ŸK Ŗ ½™BdefaultPšregulator-vdd-logicpwm-regulator Bvdd_logic Ā›Ź Ē Ņ{ ę”Qew~š™p§ sound!rockchip,rockchip-audio-max98090BdefaultPœ łVEYRON-I2S ž Ÿ 5M KM  b  y”regulator-backlightregulator-fixed Ŗ ½“ BdefaultP¢Bbacklight_regulator Ÿ :˜š§regulator-panelregulator-fixed Ŗ ½ BdefaultP£Bpanel_regulator ŸšØvcc18-lcdregulator-fixed Ŗ ½“ BdefaultP¤ Bvcc18_lcdQe Ÿbacklightpwm-backlight ž’ °’ Ē€ ą BdefaultP„ ¦B@ ķ    §š©panelinnolux,n116bge|okay Ø ©panel-timingŚl÷ *V 2ˆ ?< K U b j w  ƒ  portsportendpoint Ŗšzgpio-charger gpio-charger šmains Å1BdefaultP«lid-switch gpio-keysBdefaultP¬switch-lid gLid Å1q m § xregulator-vccsysregulator-fixedBvccsyseQš—regulator-vcc5-host1regulator-fixed Ŗ ½1 BdefaultP­ Bvcc5_host1Qeregulator-vcc5v-otgregulator-fixed Ŗ ½1 BdefaultP® Bvcc5_host2Qe #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7gpio8i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltclock-latency-nsrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplydisable-wppinctrl-namespinctrl-0cap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablemarvell,caldata-txpwrlimit-2gmarvell,caldata-txpwrlimit-5g-sub0marvell,caldata-txpwrlimit-5g-sub1marvell,caldata-txpwrlimit-5g-sub2mmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcehid-descr-addrreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsgpio-line-namesrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecstartup-delay-usbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-type