Ð þíF8h(Þ0 #,Arm Morello Fixed Virtual Platform2arm,morello-fvparm,morelloclock-50000000 2fixed-clock=Júð€ Zapb_pclkm clock-85000000 2fixed-clock=Jÿ@ Ziofpga:aclkcpus cpu@0 2arm,rainieruycpu…psci“ @²¿Ì@Þëül2-cache2cache•¢@´ëmcpu@100 2arm,rainieruycpu…psci“ @²¿Ì@Þëül2-cache2cache•¢@´ëmcpu@10000 2arm,rainieruycpu…psci“ @²¿Ì@Þëül2-cache2cache•¢@´ëmcpu@10100 2arm,rainieruycpu…psci“ @²¿Ì@Þëül2-cache2cache•¢@´ëml3-cache2cache•mfirmwarescmi 2arm,scmitxrx(/  protocol@13u=mprotocol@14u=memory@80000000ymemoryu€memory@8080000000ymemoryu€€xpmu2arm,rainier-pmu 5psci 2arm,psci-0.2Œsmcreserved-memory @secure-firmware@ff000000uÿGspe-pmu'2arm,statistical-profiling-extension-v1 5soc 2simple-bus @serial@2a4000002arm,pl011arm,primecellu*@ 5?ü Nuartclkapb_pclkZokayinterrupt-controller@30000000 2arm,gic-v3 u00  5 ar @mmsi-controller@300400002arm,gic-v3-itsu0‡–msi-controller@300600002arm,gic-v3-itsu0‡–msi-controller@300800002arm,gic-v3-itsu0‡–msi-controller@300a00002arm,gic-v3-itsu0 ‡–iommu@2ce00000 2arm,smmu-v3u,à$5LPN¡eventqgerrorcmdq-sync±mhu@450000002arm,mhu-doorbellarm,primecelluE5><¾ü  Napb_pclkmsram@6000000 2mmio-sramu€@€ scp-sram@02arm,scmi-shmemu€m scp-sram@802arm,scmi-shmemu€€m timer2arm,armv8-timer05   aliasesÊ/soc/serial@2a400000chosenÒserial0:115200n8clock-24000000 2fixed-clock=Jn6Zbp:clock24mhzm virtio_block@1c170000 2virtio,mmiou 5`virtio_net@1c180000 2virtio,mmiou 5fvirtio_rng@1c190000 2virtio,mmiou 5evirtio_p9@1c1a0000 2virtio,mmiou 5gkmi@1c1500002arm,pl050arm,primecellu 5cü NKMIREFCLKapb_pclkkmi@1c1600002arm,pl050arm,primecellu 5dü NKMIREFCLKapb_pclkethernet@1d1000002smsc,lan91c111u 5b interrupt-parent#address-cells#size-cellsmodelcompatible#clock-cellsclock-frequencyclock-output-namesphandleregdevice_typeenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheclockscache-levelcache-unifiedmbox-namesmboxesshmeminterruptsrangesno-mapclock-namesstatus#interrupt-cellsinterrupt-controllermsi-controller#msi-cellsinterrupt-names#iommu-cells#mbox-cellsserial0stdout-path