L8=("=-google,ciri-sku0google,cirimediatek,mt8188 +7Google Ciri sku0 boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dsc@1c009000T/soc/ethdr@1c114000[/soc/mailbox@10320000`/soc/mailbox@10330000e/soc/merge0@1c014000l/soc/merge@1c10c000s/soc/merge@1c10d000z/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000/soc/rdma@1c107000/soc/rdma@1c108000/soc/rdma@1c109000'/soc/rdma@1c10a0002/soc/rdma@1c10b000=/soc/dsi@1c008000B/soc/i2c@11280000G/soc/i2c@11e00000L/soc/i2c@11281000Q/soc/i2c@11282000V/soc/i2c@11e01000[/soc/i2c@11ec0000`/soc/i2c@11ec1000e/soc/mmc@11230000j/soc/serial@11001100cpus+cpu@0rcpuarm,cortex-a55~psciw5@@,@O cpu@100rcpuarm,cortex-a55~psciw5@@,@O cpu@200rcpuarm,cortex-a55~psciw5@@,@O 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maindma+JokayQdefault_ti2c@11ec1000mediatek,mt8188-i2c ~"- s/7 maindma+JokayQdefault_uclock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en~ Osefuse@11f20000%mediatek,mt8188-efusemediatek,efuse~+dp-calib@1a0~ Olvts1-calib@1ac~@ONgpu-speedbin@581~ Owsocinfo-data1@7a0~socinfo-data2@7e0~gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm~@v0-~} .jobmmugpuw speed-bin !xdCCC 5core0core1core2@Jokay H,O)clock-controller@13fbf000mediatek,mt8188-mfgcfg~Ovsyscon@14000000mediatek,mt8188-vppsys0syscon~O1dma-controller@14001000mediatek,mt8188-mdp3-rdma~ T1<y yyyy _zdC f{ ~  |display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg~ 1 f{ display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr~@1" f{@display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal~P-F1 dC f{Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz~`1  f{` ~%display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp~p1# 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display@14f100002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr~3$ f{ display@14f120002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal~ -j3#dC f{ display@14f130002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aal~0-k3%dC f{ 0display@14f150002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz~P3 f{ P ~display@14f160002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz~`3 f{ ` ~display@14f180006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp~3 f{ display@14f190006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshp~3 f{ display@14f1a0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge~3dC f{ display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge~3dC f{ display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color~-u3dC f{ display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color~-v3dC f{ display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding~3dC f{ display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding~ 3dC f{ display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot~@ T3 _dC f{ @ ~display@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot~P T3 _zdC f{ P ~clock-controller@14e00000mediatek,mt8188-wpesys~O>clock-controller@14e02000mediatek,mt8188-wpesys-vpp0~ smi@14e04000mediatek,mt8188-smi-larb~@>>apbsmidC  }Osyscon@14f00000mediatek,mt8188-vppsys1syscon~O3mutex@14f01000mediatek,mt8188-vpp-mutex~-{3&dC f{ smi@14f02000mediatek,mt8188-smi-larb~ 33apbsmidC  Osmi@14f03000mediatek,mt8188-smi-larb~033apbsmidC  }Oclock-controller@15000000mediatek,mt8188-imgsys~clock-controller@15110000 mediatek,mt8188-imgsys1-dip-top~clock-controller@15130000mediatek,mt8188-imgsys1-dip-nr~clock-controller@15220000mediatek,mt8188-imgsys-wpe1~"clock-controller@15330000mediatek,mt8188-ipesys~3clock-controller@15520000mediatek,mt8188-imgsys-wpe2~Rclock-controller@15620000mediatek,mt8188-imgsys-wpe3~bclock-controller@16000000mediatek,mt8188-camsys~O7clock-controller@1604f000mediatek,mt8188-camsys-rawa~O:clock-controller@1606f000mediatek,mt8188-camsys-yuva~O;clock-controller@1608f000mediatek,mt8188-camsys-rawb~O8clock-controller@160af000mediatek,mt8188-camsys-yuvb~ O9clock-controller@17200000mediatek,mt8188-ccusys~ video-decoder@18000000mediatek,mt8188-vcodec-dec ~@O` _z+ |video-codec@10000mediatek,mtk-vcodec-lat~$.44.x .444.xselvdeclattop-H _zzzzzzzzzdCvideo-codec@25000mediatek,mtk-vcodec-core~P$.44.x .455.xselvdeclattop-X _dCsmi@1800d000mediatek,mt8188-smi-larb~44apbsmidC  }Oclock-controller@1800f000mediatek,mt8188-vdecsys-soc~O4smi@1802e000mediatek,mt8188-smi-larb~55apbsmidC  Oclock-controller@1802f000mediatek,mt8188-vdecsys~O5clock-controller@1a000000mediatek,mt8188-vencsys~O=smi@1a010000mediatek,mt8188-smi-larb~==apbsmidC  Ovideo-encoder@1a020000mediatek,mt8188-vcodec-enc~+$.34.p= venc_sel-aX _dC |jpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc~=jpgenc-b _dCjpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec~==jpgdec-smijpgdec-c0 _dCovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl~2-| _dC fyports+port@0~endpoint Oport@1~endpoint Ordma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma~ 2-~ _z dC fy ports+port@0~endpoint Oport@1~endpoint Ocolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color~02-dC fy0ports+port@0~endpoint Oport@1~endpoint Occorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr~@2-dC fy@ports+port@0~endpoint Oport@1~endpoint Oaal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aal~P2 -dC fyPports+port@0~endpoint Oport@1~endpoint Ogamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma~`2-dC fy`ports+port@0~endpoint Oport@1~endpoint Odither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-dither~p2-dC fypports+port@0~endpoint Oport@1~endpoint Odsi@1c008000mediatek,mt8188-dsi~22enginedigitalhs- dphydCr2Jokay+panel@0~ +Qdefault_     Jokayboe,nv110wum-l60himax,hx83102portendpoint Oports+port@0~endpoint Oport@1~endpoint Odsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc~2 -dC fydsi@1c012000mediatek,mt8188-dsi~ 2 2enginedigitalhs- dphydCr2  Jdisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~@2 <mergemerge_async-dC fy@dp-intf@1c015000mediatek,mt8188-dp-intf~P2 2 -pixelenginepll-dC Jdisabledmutex@1c016000mediatek,mt8188-disp-mutex~`2-dC fy` ~>postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask~2-dC fyports+port@0~endpoint Oport@1~endpoint Osyscon@1c01d000mediatek,mt8188-vdosys0syscon~ y fyO2port+endpoint@0~ Osmi@1c022000mediatek,mt8188-smi-larb~ 22apbsmidC  Osmi@1c023000mediatek,mt8188-smi-larb~022apbsmidC  }O~smi@1c024000mediatek,mt8188-smi-common-vdo~@22apbsmidCOiommu@1c028000mediatek,mt8188-iommu-vdo~P2bclk-dCK Osyscon@1c100000mediatek,mt8188-vdosys1syscon~ y fyO<port+endpoint@1~ Omutex@1c101000mediatek,mt8188-disp-mutex~<-dC fy ~smi@1c102000mediatek,mt8188-smi-larb~ <<apbsmidC  Osmi@1c103000mediatek,mt8188-smi-larb~0<<apbsmidC  }Ordma@1c1040004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~@<- _@dC T fy@rdma@1c1050004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~P<- _z`dC T fyPrdma@1c1060004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~`<- _AdC T fy`rdma@1c1070004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~p<- _zadC T fyprdma@1c1080004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~<- _BdC T fyrdma@1c1090004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~<- _zbdC T fyrdma@1c10a0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~<- _CdC T fyrdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~<- _zcdC T fymerge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~< <mergemerge_async-dCr< fy "merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~< <mergemerge_async-dCr< fy "merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~< <mergemerge_async-dCr< fy "merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~< <mergemerge_async-dCr< fy "merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~< <mergemerge_async-dCr< fy 6ports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Odp-intf@1c113000mediatek,mt8188-dp-intf~0<:<-pixelenginepll-dCJokayports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Oethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp~@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh<0<+<.<,</<-<<<1<2<3<4<5.mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top-6 _zdzedC(r<1<2<3<4<5p fy@yPypyyyyports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Opadding@1c11d000mediatek,mt8188-disp-padding~<dC fypadding@1c11e000mediatek,mt8188-disp-padding~< dC fypadding@1c11f000mediatek,mt8188-disp-padding~<!dC fypadding@1c120000mediatek,mt8188-disp-padding~<"dC fypadding@1c121000mediatek,mt8188-disp-padding~<#dC fypadding@1c122000mediatek,mt8188-disp-padding~ <$dC fy padding@1c123000mediatek,mt8188-disp-padding~0<%dC fy0padding@1c124000mediatek,mt8188-disp-padding~@<&dC fy@edp-tx@1c500000mediatek,mt8188-edp-tx~P-dp_calibration_datadC M Jdisableddp-tx@1c600000mediatek,mt8188-dp-tx~`-dp_calibration_datadC MJokayQdefault_Oports+port@0~endpoint Oport@1~endpoint ^backlight-lcd0pwm-backlight i {@ +    Ochosen serial0:115200n8dmic-codec dmic-codec  dmemory@40000000rmemory~@regulator-pp1800-ldo-z1regulator-fixed9pp1800_ldo_z1 Hw@`w@ iregulator-pp3300-s3regulator-fixed 9pp3300_s3 H2Z`2Z iOWregulator-pp3300-z1regulator-fixed 9pp3300_z1 H2Z`2Z Oiregulator-pp3300-wlanregulator-fixed 9pp3300_wlanH2Z`2Z + _Qdefault iregulator-pp4200-s5regulator-fixed 9pp4200_s5 H@@`@@ regulator-pp5000-z1regulator-fixed 9pp5000_z1 HLK@`LK@ Oregulator-pp5000-usb-vbusregulator-fixed9pp5000_usb_vbusHLK@`LK@ + OXregulator-ppvar-sysregulator-fixed 9ppvar_sys Oregulator-ppvar-mipi-disp-avddregulator-fixed9ppvar_mipi_disp_avdd +Qdefault_ Oregulator-ppvar-mipi-disp-aveeregulator-fixed9ppvar_mipi_disp_aveex' +Qdefault_ Oreserved-memory+Omemory@55000000shared-dma-pool~U@memory@60000000shared-dma-pool~`OImemory@60f00000shared-dma-pool~`OEmemory@61000000shared-dma-pool~aOH compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0pinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5mediatek,adspaudio-routinglink-namedai-formatmediatek,clk-providersound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-downinput-enabledrive-strengthoutput-highbias-disableoutput-lowbias-pull-up#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadregulator-microvolt-offsetassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsresetsreset-namesmediatek,topckgenmemory-regionmediatek,etdm-out1-cowork-sourcemediatek,etdm-in2-cowork-sourcemboxesmbox-namesspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdno-sdionon-removablesupports-cqevmmc-supplyvqmmc-supplyclock-divAVDD-supplyDBVDD-supplyLDO1-IN-supplyMICVDD-supplyrealtek,jd-srcsound-name-prefixreset-gpiosusb2-lpm-disablebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsdrive-strength-microampbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointenable-gpiosbacklightavdd-supplyavee-supplypp1800-supplyrotationmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanesbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msregulator-boot-onvin-supplyenable-active-highgpiono-map