J8<( <-google,ciri-sku5google,cirimediatek,mt8188 +7Google Ciri sku5 board (rev4)aliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dsc@1c009000T/soc/ethdr@1c114000[/soc/mailbox@10320000`/soc/mailbox@10330000e/soc/merge0@1c014000l/soc/merge@1c10c000s/soc/merge@1c10d000z/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000/soc/rdma@1c107000/soc/rdma@1c108000/soc/rdma@1c109000'/soc/rdma@1c10a0002/soc/rdma@1c10b000=/soc/dsi@1c008000B/soc/i2c@11280000G/soc/i2c@11e00000L/soc/i2c@11281000Q/soc/i2c@11282000V/soc/i2c@11e01000[/soc/i2c@11ec0000`/soc/i2c@11ec1000e/soc/mmc@11230000j/soc/serial@11001100cpus+cpu@0rcpuarm,cortex-a55~psciw5@@,@O cpu@100rcpuarm,cortex-a55~psciw5@@,@O cpu@200rcpuarm,cortex-a55~psciw5@@,@O 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arm,psci-1.0smcsound8Jokay]Qaud_etdm_hp_onaud_etdm_hp_offaud_etdm_spk_onaud_etdm_spk_offaud_mtkaif_onaud_mtkaif_off_is}mediatek,mt8188-es83267mt8188_tas2563_8326ETDM1_OUTETDM_SPK_PINETDM2_OUTETDM_HP_PINETDM1_INETDM_SPK_PINETDM2_INETDM_HP_PINADDA CaptureMTKAIF_PINHeadphone JackHPOLHeadphone JackHPORMIC1Headset Micdai-link-0 ETDM1_IN_BEi2scpudai-link-1 ETDM1_OUT_BEi2scpucodecdai-link-2 ETDM2_IN_BEcpucodecdai-link-3 ETDM2_OUT_BEcpucodecdai-link-4DPTX_BEcodecthermal-zonescpu-little0-thermaltripstrip-alert0 _,ypassiveO trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07 H< cpu-little1-thermaltripstrip-alert0 _,ypassiveO!trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07!H< cpu-little2-thermaltripstrip-alert0 _,ypassiveO"trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07"H< cpu-little3-thermaltripstrip-alert0 _,ypassiveO#trip-alert1 s,yhottrip-crit , ycriticalcooling-mapsmap07#H< cpu-big0-thermaldtripstrip-alert0 _,ypassiveO$trip-alert1 s,yhottrip-crit , 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Ointerrupt-partition-1Osyscon@10000000 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macippcO*?+-$--4-v>->sys_ckref_ckmcu_ckd UpJokay host Vusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci~mac-$-.4-v>sys_ckJokay Yusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 ~+-+> macippcO+?+-$-,4-v>->sys_ckref_ckmcu_cke U`Jokay host Vusb@0'mediatek,mt8188-xhcimediatek,mtk-xhci~mac-$-+4-v>sys_ckJokay "fpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie~/  pcie-macO  jrpci t+0.L.#.&.+.C> /pl_250mtl_26mtl_96mtl_32kperi_26mperi_memp-` gggg  h i pcie-phydBrCymacJokayQdefault_jinterrupt-controllerpOgspi@1132c000(mediatek,mt8188-normediatek,mt8186-nor~2-X>> spisfaxi$-X-9+JokayQdefault_kflash@0jedec,spi-nor~ut-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3O+dBJokaypcie-phy@0~-ref Oidsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx~A mipi_tx0_pll Jokay POdsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx~A mipi_tx0_pll  JdisabledOi2c@11e00000mediatek,mt8188-i2c ~"- l.7 maindma+JokayQdefault_mtpm@50 google,cr50~P *Qdefault_ni2c@11e01000mediatek,mt8188-i2c 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display@14f1b0006mediatek,mt8188-mdp3-mergemediatek,mt8195-mdp3-merge~2dB 6x display@14f1d0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color~-u2dB 6x display@14f1e0006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color~-v2dB 6x display@14f21000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding~2dB 6x display@14f22000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding~ 2dB 6x display@14f240004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot~@ $2 /dB 6x @ Ndisplay@14f250004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot~P $2 /wdB 6x P Nclock-controller@14e00000mediatek,mt8188-wpesys~O=clock-controller@14e02000mediatek,mt8188-wpesys-vpp0~ smi@14e04000mediatek,mt8188-smi-larb~@==apbsmidB o zOsyscon@14f00000mediatek,mt8188-vppsys1syscon~O2mutex@14f01000mediatek,mt8188-vpp-mutex~-{2&dB 6x smi@14f02000mediatek,mt8188-smi-larb~ 22apbsmidB o Osmi@14f03000mediatek,mt8188-smi-larb~022apbsmidB o zO~clock-controller@15000000mediatek,mt8188-imgsys~clock-controller@15110000 mediatek,mt8188-imgsys1-dip-top~clock-controller@15130000mediatek,mt8188-imgsys1-dip-nr~clock-controller@15220000mediatek,mt8188-imgsys-wpe1~"clock-controller@15330000mediatek,mt8188-ipesys~3clock-controller@15520000mediatek,mt8188-imgsys-wpe2~Rclock-controller@15620000mediatek,mt8188-imgsys-wpe3~bclock-controller@16000000mediatek,mt8188-camsys~O6clock-controller@1604f000mediatek,mt8188-camsys-rawa~O9clock-controller@1606f000mediatek,mt8188-camsys-yuva~O:clock-controller@1608f000mediatek,mt8188-camsys-rawb~O7clock-controller@160af000mediatek,mt8188-camsys-yuvb~ O8clock-controller@17200000mediatek,mt8188-ccusys~ video-decoder@18000000mediatek,mt8188-vcodec-dec ~@O` /w+ byvideo-codec@10000mediatek,mtk-vcodec-lat~$-44-x -433-xselvdeclattop-H /wwwwwwwwwdBvideo-codec@25000mediatek,mtk-vcodec-core~P$-44-x -444-xselvdeclattop-X /dBsmi@1800d000mediatek,mt8188-smi-larb~33apbsmidB o zOclock-controller@1800f000mediatek,mt8188-vdecsys-soc~O3smi@1802e000mediatek,mt8188-smi-larb~44apbsmidB o Oclock-controller@1802f000mediatek,mt8188-vdecsys~O4clock-controller@1a000000mediatek,mt8188-vencsys~O<smi@1a010000mediatek,mt8188-smi-larb~<<apbsmidB o Ovideo-encoder@1a020000mediatek,mt8188-vcodec-enc~+$-34-p< venc_sel-aX /dB byjpeg-encoder@1a030000+mediatek,mt8188-jpgencmediatek,mtk-jpgenc~<jpgenc-b /dBjpeg-decoder@1a040000.mediatek,mt8188-jpgdecmediatek,mt2701-jpgdec~<<jpgdec-smijpgdec-c0 /dBovl@1c0000002mediatek,mt8188-disp-ovlmediatek,mt8195-disp-ovl~1-| /dB 6vports+port@0~endpoint Oport@1~endpoint Ordma@1c0020004mediatek,mt8188-disp-rdmamediatek,mt8195-disp-rdma~ 1-~ /w dB 6v ports+port@0~endpoint Oport@1~endpoint Ocolor@1c0030006mediatek,mt8188-disp-colormediatek,mt8173-disp-color~01-dB 6v0ports+port@0~endpoint Oport@1~endpoint Occorr@1c0040006mediatek,mt8188-disp-ccorrmediatek,mt8192-disp-ccorr~@1-dB 6v@ports+port@0~endpoint Oport@1~endpoint Oaal@1c0050002mediatek,mt8188-disp-aalmediatek,mt8183-disp-aal~P1 -dB 6vPports+port@0~endpoint Oport@1~endpoint Ogamma@1c0060006mediatek,mt8188-disp-gammamediatek,mt8195-disp-gamma~`1-dB 6v`ports+port@0~endpoint Oport@1~endpoint Odither@1c0070008mediatek,mt8188-disp-dithermediatek,mt8183-disp-dither~p1-dB 6vpports+port@0~endpoint Oport@1~endpoint Odsi@1c008000mediatek,mt8188-dsi~11enginedigitalhs- dphydBr1Jokay+panel@0~ *Qdefault_     Jokayivo,t109nw41himax,hx83102portendpoint Oports+port@0~endpoint Oport@1~endpoint Odsc@1c0090002mediatek,mt8188-disp-dscmediatek,mt8195-disp-dsc~1 -dB 6vdsi@1c012000mediatek,mt8188-dsi~ 1 1enginedigitalhs- dphydBr1  Jdisabledmerge0@1c0140006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~@1 ;mergemerge_async-dB 6v@dp-intf@1c015000mediatek,mt8188-dp-intf~P1 1 ,pixelenginepll-dB Jdisabledmutex@1c016000mediatek,mt8188-disp-mutex~`1-dB 6v` N>postmask@1c01a000<mediatek,mt8188-disp-postmaskmediatek,mt8192-disp-postmask~1-dB 6vports+port@0~endpoint Oport@1~endpoint Osyscon@1c01d000mediatek,mt8188-vdosys0syscon~ v 6vO1port+endpoint@0~ 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6vrdma@1c10b0004mediatek,mt8188-vdo1-rdmamediatek,mt8195-vdo1-rdma~;- /wcdB $ 6vmerge@1c10c0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-dBr; 6v merge@1c10d0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-dBr; 6v merge@1c10e0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-dBr; 6v merge@1c10f0006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-dBr; 6v merge@1c1100006mediatek,mt8188-disp-mergemediatek,mt8195-disp-merge~; ;mergemerge_async-dBr; 6v ports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Odp-intf@1c113000mediatek,mt8188-dp-intf~0;:;,pixelenginepll-dBJokayports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Oethdr@1c1140006mediatek,mt8188-disp-ethdrmediatek,mt8195-disp-ethdrp~@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsh;0;+;.;,;/;-;<;1;2;3;4;5-mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top-6 /wdwedB(r;1;2;3;4;5p 6v@vPvpvvvvports+port@0+~endpoint@1~ Oport@1+~endpoint@1~ Opadding@1c11d000mediatek,mt8188-disp-padding~;dB 6vpadding@1c11e000mediatek,mt8188-disp-padding~; dB 6vpadding@1c11f000mediatek,mt8188-disp-padding~;!dB 6vpadding@1c120000mediatek,mt8188-disp-padding~;"dB 6vpadding@1c121000mediatek,mt8188-disp-padding~;#dB 6vpadding@1c122000mediatek,mt8188-disp-padding~ ;$dB 6v padding@1c123000mediatek,mt8188-disp-padding~0;%dB 6v0padding@1c124000mediatek,mt8188-disp-padding~@;&dB 6v@edp-tx@1c500000mediatek,mt8188-edp-tx~P-dp_calibration_datadB  Jdisableddp-tx@1c600000mediatek,mt8188-dp-tx~`-dp_calibration_datadB JokayQdefault_Oports+port@0~endpoint Oport@1~endpoint .backlight-lcd0pwm-backlight 9 K@ * d {  Ochosen serial0:115200n8dmic-codec dmic-codec  dmemory@40000000rmemory~@regulator-pp1800-ldo-z1regulator-fixed9pp1800_ldo_z1 Hw@`w@ fregulator-pp3300-s3regulator-fixed 9pp3300_s3 H2Z`2Z fOVregulator-pp3300-z1regulator-fixed 9pp3300_z1 H2Z`2Z Ofregulator-pp3300-wlanregulator-fixed 9pp3300_wlanH2Z`2Z  * _Qdefault fregulator-pp4200-s5regulator-fixed 9pp4200_s5 H@@`@@ regulator-pp5000-z1regulator-fixed 9pp5000_z1 HLK@`LK@ Oregulator-pp5000-usb-vbusregulator-fixed9pp5000_usb_vbusHLK@`LK@  * OWregulator-ppvar-sysregulator-fixed 9ppvar_sys Oregulator-ppvar-mipi-disp-avddregulator-fixed9ppvar_mipi_disp_avdd  *Qdefault_ Oregulator-ppvar-mipi-disp-aveeregulator-fixed9ppvar_mipi_disp_aveex'  *Qdefault_ Oreserved-memory+Omemory@55000000shared-dma-pool~U@memory@60000000shared-dma-pool~` OHmemory@60f00000shared-dma-pool~` ODmemory@61000000shared-dma-pool~a OG compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1dsc0ethdr0gce0gce1merge0merge1merge2merge3merge4merge5mutex0mutex1padding0padding1padding2padding3padding4padding5padding6padding7vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7dsi0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0serial0device_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheperformance-domains#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsmediatek,platformstatuspinctrl-namespinctrl-0pinctrl-1pinctrl-2pinctrl-3pinctrl-4pinctrl-5mediatek,adspaudio-routinglink-namedai-formatmediatek,clk-providersound-daipolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicedma-ranges#performance-domain-cells#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxbias-pull-downinput-enabledrive-strengthoutput-highbias-disableoutput-lowbias-pull-up#power-domain-cellsdomain-supplyclocksclock-namesmediatek,infracfgmediatek,disable-extrst#sound-dai-cellsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadregulator-microvolt-offsetassigned-clocksassigned-clock-parents#iommu-cells#mbox-cellspower-domainsresetsreset-namesmediatek,topckgenmemory-regionmediatek,etdm-out1-cowork-sourcemediatek,etdm-in2-cowork-sourcemboxesmbox-namesspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsphyswakeup-sourcemediatek,syscon-wakeupdr_modevusb33-supplyvbus-supplyinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,prioritysnps,weightbus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdno-sdionon-removablesupports-cqevmmc-supplyvqmmc-supplyclock-diveverest,jack-poleverest,interrupt-clkreset-gpiosusb2-lpm-disablebus-rangelinux,pci-domaininterrupt-mapinterrupt-map-maskiommu-mapiommu-map-maskphy-names#phy-cellsdrive-strength-microampbitsoperating-points-v2power-domain-namesmali-supply#dma-cellsiommusmediatek,gce-client-regmediatek,gce-eventsmediatek,scpmediatek,larb-idmediatek,smimediatek,larbsremote-endpointenable-gpiosbacklightavdd-supplyavee-supplypp1800-supplyrotationmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanesbrightness-levelsdefault-brightness-levelnum-interpolated-stepspower-supplypwmsstdout-pathnum-channelswakeup-delay-msregulator-boot-onvin-supplyenable-active-highgpiono-map