F88(84mediatek,mt8370-evkmediatek,mt8370mediatek,mt8188 +7MediaTek Genio-510 EVKaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/dsc@1c009000T/soc/ethdr@1c114000[/soc/mailbox@10320000`/soc/mailbox@10330000e/soc/merge0@1c014000l/soc/merge@1c10c000s/soc/merge@1c10d000z/soc/merge@1c10e000/soc/merge@1c10f000/soc/merge@1c110000/soc/mutex@1c016000/soc/mutex@1c101000/soc/padding@1c11d000/soc/padding@1c11e000/soc/padding@1c11f000/soc/padding@1c120000/soc/padding@1c121000/soc/padding@1c122000/soc/padding@1c123000/soc/padding@1c124000/soc/rdma@1c104000/soc/rdma@1c105000/soc/rdma@1c106000/soc/rdma@1c107000/soc/rdma@1c108000/soc/rdma@1c109000'/soc/rdma@1c10a0002/soc/rdma@1c10b000=/soc/dsi@1c008000B/soc/ethernet@11021000L/soc/i2c@11280000Q/soc/i2c@11e00000V/soc/i2c@11281000[/soc/i2c@11282000`/soc/i2c@11e01000e/soc/i2c@11ec0000j/soc/i2c@11ec1000o/soc/mmc@11230000t/soc/mmc@11240000y/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55psciw5@ @*;O^ cpu@100cpuarm,cortex-a55psciw5@ @*;O^ cpu@200cpuarm,cortex-a55psciw5@ @*;O^ cpu@300cpuarm,cortex-a55psciw5@ @*;O^ cpu@600cpuarm,cortex-a78psci!V@ @*;O^ cpu@700cpuarm,cortex-a78psci!V@ @*;O^cpu-mapcluster0core0f core1f core2f core3f core6f core7fidle-statesjpscicpu-off-larm,idle-statew2_D^cpu-off-barm,idle-statew-^cluster-off-larm,idle-statew7H^cluster-off-barm,idle-statew2^l2-cache0cache@*^l2-cache1cache@*^l3-cachecache @^oscillator-13m fixed-clock]@clk13m^7oscillator-26m fixed-clockclk26m^9oscillator-32k fixed-clockclk32kopp-table-gpuoperating-points-v2 ^opp-390000000>+opp-431000000+opp-4730000001h@ '+opp-515000000F X+opp-556000000!# h+opp-598000000# <+opp-640000000&% +opp-670000000'c +opp-700000000)' L+opp-730000000+ }+opp-760000000-L `+opp-790000000/q 4+opp-8350000001 (r+opp-8800000004s q+opp-9150000006 X+opp-915000000-56 +0opp-915000000-66 q+popp-9500000008ـ 5+opp-950000000-58ـ X+0opp-950000000-68ـ q+ppmu-a55arm,cortex-a55-pmu <pmu-a78arm,cortex-a78-pmu <psci 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mediatek,mt8188-topckgensyscon^%syscon@10001000#mediatek,mt8188-infracfg-aosysconr^&syscon@10003000mediatek,mt8188-pericfgsyscon0^Ipinctrl@10005000mediatek,mt8188-pinctrl`P0iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint"T<,^"audio-default-pins^pins-cmd-datXefghijklmnrstuvyz|}~disp-pwm1-pins^Epins-pwmdptx-pinspins-cmd-dat.edp-panel-3v3-en-pins^pins1eth-default-pins^Upins-ccpins-mdiopins-powerpins-rxdpins-txdeth-sleep-pins^Vpins-ccpins-mdiopins-rxdpins-txdi2c0-pins^`pins87i2c1-pins^rpins:9i2c2-pins^dpins<;i2c3-pins^epins>=i2c4-pins^upins@?i2c5-pins^|pinsBAi2c6-pins^}pinsDCgpio-key-pinspins *+,mmc0-default-pins^Wpins-clk fpins-cmd-dat$epins-rstemmc0-uhs-pins^Xpins-clk fpins-cmd-dat$epins-ds fpins-rstemmc1-default-pins^[pins-clk fpins-cmd-datepins-insertmmc1-uhs-pins^\pins-clk fpins-cmd-datemmc2-default-pinspins-clk fpins-cmd-datepins-pcm{mmc2-uhs-pinspins-clk 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css-pextp-fmem:power-domain@7\%0%1cseninf0seninf1:power-domain@6:power-domain@10 \%E%D cbusmaino&+:power-domain@11 o&+:power-domain@14\%Fcasmo&:power-domain@13 \%S%6ca1sysintbusadspcko&:power-domain@12 o&:power-domain@8\5  cethermaco&:watchdog@10007000mediatek,mt8188-wdtpr^;syscon@1000c000"mediatek,mt8188-apmixedsyssyscon^$timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerp< \7pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsyscon@pwrap<\&& cspiwrappmicmediatek,mt6359T, "<^adcmediatek,mt6359-auxadcaudio-codecmediatek,mt6359-codecregulatorsmediatek,mt6359-regulatorbuck_vs1vs1 5 !#?buck_vgpu11 dvdd_core 7S# h?buck_vmodemvmodem S*#buck_vpu dvdd_adsp 7S# h?buck_vcore dvdd_proc_l  S# h?buck_vs2vs2 5 j#?buck_vpavpa_pmu  /M`#,^]buck_vproc2vgpudp 5SL# h'j^#buck_vproc1vproc1 7SL# hbuck_vcore_sshub vcore_sshub 7buck_vgpu11_sshub vgpu11_sshub 7ldo_vaud18vaud18w@ w@#ldo_vsim1 vsim1_pmu /M`#^^ldo_vibrvibrO 2Zldo_vrf12va12_abb2_pmu  ?ldo_vusbvusb- -#?^Jldo_vsram_proc2 vsram_proc2  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%\&&%8(cpmif_sys_ckpmif_tmr_ckspmimst_clk_muxiommu@10315000mediatek,mt8188-iommu-infra1P<$^nmailbox@10320000mediatek,mt8188-gce2@<1\&^mailbox@10330000mediatek,mt8188-gce3@<1\&^scp@10720000mediatek,mt8188-scp-dualrcfg+ PYokayscp@0mediatek,scp-core sram<Yokay=8^scp@d0000mediatek,scp-core sram< Ydisabledaudio-controller@10b10000mediatek,mt8188-afe%S %\9$ $ %%%%%%S%% %E%Q%M%N%O%P6%%%%T%Rcclk26mapll1apll2apll12_div0apll12_div1apll12_div2apll12_div3apll12_div9top_a1sys_hptop_aud_intbustop_audio_htop_audio_local_bustop_dptxtop_i2so1top_i2so2top_i2si1top_i2si2adsp_audio_26mapll1_d4apll2_d4apll12_div4top_a2systop_aud_iec<6K: Y; `audiosyso&l%Yokay=<^adsp@10b80000mediatek,mt8188-dsp@ cfgsramsecbus%D\%D%Ecaudiodspadsp_bus~=>rxtxK: Yokay=?@^mailbox@10b861004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxa<1^=mailbox@10b871004mediatek,mt8188-adsp-mboxmediatek,mt8186-adsp-mboxq<1^>clock-controller@10b91100mediatek,mt8188-adsp-audio26m^6serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uart< \9& cbaudbusYokaynA`defaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uart< \9& cbaudbusYokaynB`defaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uart< \9& cbaudbusYokaynC`defaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uart< \9& cbaudbus Ydisabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadc \&cmain Ydisabledsyscon@11003000"mediatek,mt8188-pericfg-aosyscon0^5spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+<\%y%&cparent-clksel-clkspi-clk Ydisabledthermal-sensor@1100b000mediatek,mt8188-lvts-ap <\&Y&Dlvts-calib-data-1^pwm@1100e0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm\%'&/cmainmm< Ydisabledpwm@1100f0002mediatek,mt8188-disp-pwmmediatek,mt8183-disp-pwm\%(&Fcmainmm<Yokay`defaultnE^spi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+<\%y%&2cparent-clksel-clkspi-clk Ydisabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+ 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0iusb@112b1000#mediatek,mt8188-mtu3mediatek,mtu3 +-+> macippc +?+<%, %v\5%5csys_ckref_ckmcu_ckj I`Yokayotg high-speedJnk`defaultusb@0'mediatek,mt8188-xhcimediatek,mtk-xhcimac<%+ %v\5csys_ckYokayconnector%gpio-usb-b-connectorusb-b-connectormicro <"S 0lpcie@112f0000*mediatek,mt8188-pciemediatek,mt8192-pcie/  pcie-mac  Epci O+0\&L&#&&&+&C5 /cpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem,<` `mmmm n n o pcie-phyK:Y;`macYokay`defaultnpinterrupt-controller,T^mspi@1132c000(mediatek,mt8188-normediatek,mt8186-nor2\%X55 cspisfaxi%X<9+ Ydisabledt-phy@11c20700.mediatek,mt8188-tphymediatek,generic-tphy-v3 +K:Yokaypcie-phy@0\%cref ^odsi-phy@11c800000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx\9 mipi_tx0_pll Yokay^dsi-phy@11c900000mediatek,mt8188-mipi-txmediatek,mt8183-mipi-tx\9 mipi_tx0_pll  Ydisabled^i2c@11e00000mediatek,mt8188-i2c "< \q&7 cmaindma+Yokay`defaultnrtypec-mux@48 ite,it5205H   sportendpointDt^zi2c@11e01000mediatek,mt8188-i2c "< \q&7 cmaindma+Yokay`defaultnuB@rt1715@4erichtek,rt1715N " `defaultnv 0wconnectorusb-c-connector USB-C dual  dual sink  !" +"altmodesdisplayport 7 <Gports+port@0endpointDx^Pport@1endpointDy^Oport@2endpointDz^tclock-controller@11e02000mediatek,mt8188-imp-iic-wrap-w ^qt-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ Yokayusb-phy@0\%$ crefda_ref ^jt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ Yokayusb-phy@0\%$ crefda_ref ^Gusb-phy@700 \$9 crefda_ref ^Ht-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+ Yokayusb-phy@0\%$ crefda_ref ^fi2c@11ec0000mediatek,mt8188-i2c "< \{&7 cmaindma+Yokay`defaultn|i2c@11ec1000mediatek,mt8188-i2c "< \{&7 cmaindma+Yokay`defaultn}clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-en ^{efuse@11f20000%mediatek,mt8188-efusemediatek,efuse+dp-calib@1a0 ^lvts1-calib@1ac@^Dgpu-speedbin@581 @^socinfo-data1@7a0socinfo-data2@7e0gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jm@\~0<~} Tjobmmugpu speed-bin EK::: Ycore0core1core2OYokay l#^ clock-controller@13fbf000mediatek,mt8188-mfgcfg^~syscon@14000000mediatek,mt8188-vppsys0syscon^(dma-controller@14001000mediatek,mt8188-mdp3-rdma x\(<~  K:    display@140020000mediatek,mt8188-mdp3-fgmediatek,mt8195-mdp3-fg \( display@140040002mediatek,mt8188-mdp3-hdrmediatek,mt8195-mdp3-hdr@\(" @display@140050002mediatek,mt8188-mdp3-aalmediatek,mt8195-mdp3-aalP<F\( K: Pdisplay@140060002mediatek,mt8188-mdp3-rszmediatek,mt8183-mdp3-rsz`\(  ` %display@140070006mediatek,mt8188-mdp3-tdshpmediatek,mt8195-mdp3-tdshpp\(# pdisplay@140080006mediatek,mt8188-mdp3-colormediatek,mt8195-mdp3-color<I\($K: display@140090002mediatek,mt8188-mdp3-ovlmediatek,mt8195-mdp3-ovl<J\(%K:  display@1400a000:mediatek,mt8188-mdp3-paddingmediatek,mt8195-mdp3-padding\(K: display@1400b0002mediatek,mt8188-mdp3-tccmediatek,mt8195-mdp3-tcc\( display@1400c0004mediatek,mt8188-mdp3-wrotmediatek,mt8183-mdp3-wrot x\( K:   +mutex@1400f000mediatek,mt8188-vpp-mutex<P\(K: smi@14012000mediatek,mt8188-smi-common-vpp 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