8(  (,Qualcomm Technologies, Inc. QCS615 Ride2qcom,qcs615-rideqcom,qcs615 =embeddedcpus cpu@0Jcpu2arm,cortex-a55VZpscihvpscidl2-cache2cachecpu@100Jcpu2arm,cortex-a55VZpscihvpscidl2-cache2cachecpu@200Jcpu2arm,cortex-a55VZpscihvpscidl2-cache2cachecpu@300Jcpu2arm,cortex-a55VZpscih vpscid l2-cache2cache cpu@400Jcpu2arm,cortex-a55VZpscih vpscid l2-cache2cache cpu@500Jcpu2arm,cortex-a55VZpscih vpscidl2-cache2cachecpu@600Jcpu2arm,cortex-a76VZpscihvpscil2-cache2cachecpu@700Jcpu2arm,cortex-a76VZpscihvpscil2-cache2cachecpu-mapcluster0core0core1core2core3core4core5core6core7l3-cache2cachedummy-sink2arm,coresight-dummy-sinkin-portsportendpointidle-states pscicpu-sleep-0-02arm,idle-statesilver-power-collapse)@@%Qar"cpu-sleep-0-12arm,idle-statesilver-rail-power-collapse)@@Qar#cpu-sleep-1-02arm,idle-stategold-power-collapse)@@ Qar$cpu-sleep-1-12arm,idle-stategold-rail-power-collapse)@@Q>ar%domain-idle-statescluster-sleep-02domain-idle-state)AD@ Q a&cluster-sleep-12domain-idle-state)AD@ Qa!'cluster-sleep-22domain-idle-state)AD@6Qa&b(memory@80000000JmemoryVfirmwarescm2qcom,scm-qcs615qcom,scm0interconnect-02qcom,qcs615-camnoc-virtinterconnect-12qcom,qcs615-ipa-virtinterconnect-22qcom,qcs615-mc-virt1opp-table-qup2operating-points-v2Iopp-75000000xhopp-100000000opp-128000000  psci 2arm,psci-1.0asmcpower-domain-cpu0h!"#power-domain-cpu1h!"#power-domain-cpu2h!"#power-domain-cpu3h!"# power-domain-cpu4h!"# power-domain-cpu5h!"# power-domain-cpu6h!$%power-domain-cpu7h!$%power-domain-cluster &'(!reserved-memory aop-cmd-db@85f20000 2qcom,cmd-dbVsmem@86000000 2qcom,smemV  )soc@0 2simple-bus clock-controller@1000002qcom,qcs615-gccV,9**+,efuse@7800002qcom,qcs615-qfpromqcom,qfpromVxp hstx-trim@1f8V@rng@7930002qcom,qcs615-trngqcom,trngVy0mmc@7c4000$2qcom,qcs615-sdhciqcom,sdhci-msm-v50V|@|P| EhccqhciiceOZhc_irqpwr_irq 9,k,l*,njifacecorexoicev,h-}. /00 123sdhc-ddrcpu-sdhcd,ɀhokay45defaultsleep&3BQk6w7opp-table2operating-points-v2.opp-50000000opp-100000000opp-200000000 8opp-384000000` dma-controller@800000(2qcom,qcs615-gpi-dmaqcom,sdm845-gpi-dmaV`O / disabled<geniqup@8c00002qcom,geni-se-qupV`9,e,f jm-ahbs-ahb / okayserial@8800002qcom,geni-debug-uartV@9,Kjse9:default OY00123qup-corequp-configh-okayi2c@8840002qcom,geni-i2cV@@  OZ9,Mjse;defaultH012301qup-corequp-configqup-memoryh- <<txrx disabledi2c@8880002qcom,geni-i2cV@  O[9,Ojse=defaultH012301qup-corequp-configqup-memoryh- <<txrx disabledspi@8880002qcom,geni-spiV@ O[9,Ojse>?default00123qup-corequp-configh- <<txrx  disabledserial@8880002qcom,geni-uartV@ O[9,Ojse@ABCdefault00123qup-corequp-configh- disabledi2c@88c0002qcom,geni-i2cV@  O\9,QjseDdefaultH012301qup-corequp-configqup-memoryh- <<txrx disableddma-controller@a00000(2qcom,qcs615-gpi-dmaqcom,sdm845-gpi-dmaV`O%& /v disabledFgeniqup@ac00002qcom,geni-se-qupV 9,g,h jm-ahbs-ahb /c  disabledi2c@a800002qcom,geni-i2cV@9,YjseEdefault Oa H012301qup-corequp-configqup-memoryh- FFtxrx disabledspi@a800002qcom,geni-spiV@9,YjseGHdefault Oa 00123qup-corequp-configh-}I FFtxrx disabledserial@a800002qcom,geni-uartV@9,YjseJKLMdefault Oa00123qup-corequp-configh-}I disabledi2c@a840002qcom,geni-i2cV@@9,[jseNdefault Ob H012301qup-corequp-configqup-memoryh- FFtxrx disabledi2c@a880002qcom,geni-i2cV@9,]jseOdefault Oc H012301qup-corequp-configqup-memoryh- FFtxrx disabledspi@a880002qcom,geni-spiV@9,]jsePQdefault Oc 00123qup-corequp-configh-}I FFtxrx disabledserial@a880002qcom,geni-uartV@9,]jseRSTUdefault Oc00123qup-corequp-configh-}I disabledi2c@a8c0002qcom,geni-i2cV@9,_jseVdefault Od H012301qup-corequp-configqup-memoryh- FFtxrx disabledspi@a8c0002qcom,geni-spiV@9,_jseWXdefault Od 00123qup-corequp-configh-}I FFtxrx disabledserial@a8c0002qcom,geni-uartV@9,_jseYZ[\default Od00123qup-corequp-configh-}I disabledinterconnect@1500000VPP2qcom,qcs615-config-noc3interconnect@1620000Vb2qcom,qcs615-system-nocinterconnect@1700000Vp2qcom,qcs615-aggre1-noc0interconnect@1740000Vt2qcom,qcs615-mmss-nocufshc@1d84000+2qcom,qcs615-ufshcqcom,ufshcjedec,ufs-2.0 V@0Estdice O @9,~, ,},,*,,ijcore_clkbus_aggr_clkiface_clkcore_clk_uniproref_clktx_lane0_sync_clkrx_lane0_sync_clkice_core_clkv, rst}]00123%ufs-ddrcpu-ufsh, /^ufsphy,okay _{6 '/7< '`opp-table2operating-points-v2]opp-50000000@<4`xhopp-100000000@xhрopp-200000000@ р phy@1d8700002qcom,qcs615-qmp-ufs-phyqcom,sm6115-qmp-ufs-phyVp9*,,|jrefref_auxqrefh,v`ufsphyOokayZajb^dma-controller@1dc4000 2qcom,bam-v1.7.4qcom,bam-v1.7.0V@@ Oz /ccrypto@1dfa000)2qcom,qcs615-qceqcom,sm8150-qceqcom,qceVߠ`ccrxtx /01memoryhwlock@1f400002qcom,tcsr-mutexV)syscon@1fc00002qcom,qcs615-tcsrsysconVpinctrl@31000002qcom,qcs615-tlmm0V0P00Eeastwestsouth O_|d_qup-i2c1-data-clk-state gpio4gpio5$qup0;qup-i2c2-data-clk-state gpio0gpio1$qup0=qup-i2c3-data-clk-stategpio18gpio19$qup0Dqup-i2c4-data-clk-stategpio20gpio21$qup1Equp-i2c5-data-clk-stategpio14gpio15$qup1Nqup-i2c6-data-clk-state gpio6gpio7$qup1Oqup-i2c7-data-clk-stategpio10gpio11$qup1Vqup-spi2-data-clk-stategpio0gpio1gpio2$qup0>qup-spi2-cs-stategpio3$qup0?qup-spi2-cs-gpio-stategpio3$gpioqup-spi4-data-clk-stategpio20gpio21gpio22$qup1Gqup-spi4-cs-stategpio23$qup1Hqup-spi4-cs-gpio-stategpio23$gpioqup-spi6-data-clk-stategpio6gpio7gpio8$qup1Pqup-spi6-cs-stategpio9$qup1Qqup-spi6-cs-gpio-stategpio9$gpioqup-spi7-data-clk-stategpio10gpio11gpio12$qup1Wqup-spi7-cs-stategpio13$qup1Xqup-spi7-cs-gpio-stategpio13$gpioqup-uart0-tx-stategpio16$qup09qup-uart0-rx-stategpio17$qup0:qup-uart2-cts-stategpio0$qup0@qup-uart2-rts-stategpio1$qup0Aqup-uart2-tx-stategpio2$qup0Bqup-uart2-rx-stategpio3$qup0Cqup-uart4-cts-stategpio20$qup1Jqup-uart4-rts-stategpio21$qup1Kqup-uart4-tx-stategpio22$qup1Lqup-uart4-rx-stategpio23$qup1Mqup-uart6-cts-stategpio6$qup1Rqup-uart6-rts-stategpio7$qup1Squp-uart6-tx-stategpio8$qup1Tqup-uart6-rx-stategpio9$qup1Uqup-uart7-cts-stategpio10$qup1Yqup-uart7-rts-stategpio11$qup1Zqup-uart7-tx-stategpio12$qup1[qup-uart7-rx-stategpio13$qup1\sdc1-on-state4clk-pins sdc1_clk-:cmd-pins sdc1_cmdI: data-pins sdc1_dataI: rclk-pins sdc1_rclkVsdc1-off-state5clk-pins sdc1_clk-:cmd-pins sdc1_cmdI:data-pins sdc1_dataI:rclk-pins sdc1_rclkVsdc2-on-stateclk-pins sdc2_clk-:cmd-pins sdc2_cmdI: data-pins sdc2_dataI: sdc2-off-stateclk-pins sdc2_clk-:cmd-pins sdc2_cmdI:data-pins sdc2_dataI:stm@6002000 2arm,coresight-stmarm,primecell V (Estm-basestm-stimulus-base9e japb_pclkout-portsportendpointfutpda@6004000"2qcom,coresight-tpdaarm,primecellV@9e japb_pclkin-ports port@0Vendpointgport@4Vendpointhport@5Vendpointiport@6Vendpointjport@7Vendpointkport@8Vendpointlport@9V endpointmport@bV endpointnport@cV endpointoport@dV endpointpout-portsportendpointqrfunnel@6005000+2arm,coresight-dynamic-funnelarm,primecellVP9e japb_pclkin-portsportendpointrqout-portsportendpointstcti@6010000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@6011000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@6012000 2arm,coresight-ctiarm,primecellV 9e japb_pclkcti@6013000 2arm,coresight-ctiarm,primecellV09e japb_pclkcti@6014000 2arm,coresight-ctiarm,primecellV@9e japb_pclkcti@6015000 2arm,coresight-ctiarm,primecellVP9e japb_pclkcti@6016000 2arm,coresight-ctiarm,primecellV`9e japb_pclkcti@6017000 2arm,coresight-ctiarm,primecellVp9e japb_pclkcti@6018000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@6019000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@601a000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@601b000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@601c000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@601d000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@601e000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@601f000 2arm,coresight-ctiarm,primecellV9e japb_pclkfunnel@6041000+2arm,coresight-dynamic-funnelarm,primecellV9e japb_pclkin-ports port@6Vendpointtsport@7Vendpointufout-portsportendpointv{funnel@6042000+2arm,coresight-dynamic-funnelarm,primecellV 9e japb_pclkin-ports port@3Vendpointwport@4Vendpointxport@7Vendpointyout-portsportendpointz|funnel@6045000+2arm,coresight-dynamic-funnelarm,primecellVP9e japb_pclkin-ports port@0Vendpoint{vport@1Vendpoint|zout-portsportendpoint}replicator@6046000/2arm,coresight-dynamic-replicatorarm,primecellV`9e japb_pclkin-portsportendpoint~out-ports port@1Vendpointtmc@6047000 2arm,coresight-tmcarm,primecellVp9e japb_pclkin-portsportendpoint}out-portsportendpoint~replicator@604a000/2arm,coresight-dynamic-replicatorarm,primecellV9e japb_pclk disabledin-portsportendpointout-portsportendpointcti@683b000 2arm,coresight-ctiarm,primecellV9e japb_pclktpdm@6840000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke@{  disabledout-portsportendpointktpdm@684c000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke { out-portsportendpointmtpdm@6850000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke@{   out-portsportendpointptpdm@6860000"2qcom,coresight-tpdmarm,primecellV9e japb_pclk  out-portsportendpointfunnel@6861000+2arm,coresight-dynamic-funnelarm,primecellV9e japb_pclkin-portsportendpointout-portsportendpointjcti@6867000 2arm,coresight-ctiarm,primecellVp9e japb_pclktpdm@6870000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke {  disabledout-portsportendpointltpdm@699c000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke {    disabledout-portsportendpointxtpdm@69c0000"2qcom,coresight-tpdmarm,primecellV9e japb_pclk  out-portsportendpointfunnel@69c3000+2arm,coresight-dynamic-funnelarm,primecellV09e japb_pclkin-portsportendpointout-portsportendpointhtpdm@69d0000"2qcom,coresight-tpdmarm,primecellV9e japb_pclk   disabledout-portsportendpointntpdm@6a00000"2qcom,coresight-tpdmarm,primecellV9e japb_pclk   disabledout-portsportendpointcti@6a02000 2arm,coresight-ctiarm,primecellV 9e japb_pclkcti@6a03000 2arm,coresight-ctiarm,primecellV09e japb_pclkcti@6a10000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@6a11000 2arm,coresight-ctiarm,primecellV9e japb_pclkfunnel@6a05000+2arm,coresight-dynamic-funnelarm,primecellVP9e japb_pclkin-portsportendpointout-portsportendpointitpda@6b01000"2qcom,coresight-tpdaarm,primecellV9e japb_pclkin-ports port@0Vendpointport@1Vendpointout-portsportendpointtpdm@6b02000"2qcom,coresight-tpdmarm,primecellV 9e japb_pclke@{  disabledout-portsportendpointtpdm@6b03000"2qcom,coresight-tpdmarm,primecellV09e japb_pclk   disabledout-portsportendpointcti@6b04000 2arm,coresight-ctiarm,primecellV@9e japb_pclkcti@6b05000 2arm,coresight-ctiarm,primecellVP9e japb_pclkcti@6b06000 2arm,coresight-ctiarm,primecellV`9e japb_pclkcti@6b07000 2arm,coresight-ctiarm,primecellVp9e japb_pclkfunnel@6b08000+2arm,coresight-dynamic-funnelarm,primecellV9e japb_pclkin-ports port@6Vendpointport@7Vendpointout-portsportendpointtmc@6b09000 2arm,coresight-tmcarm,primecellV9e japb_pclkin-portsportendpointout-portsportendpointreplicator@6b0a000/2arm,coresight-dynamic-replicatorarm,primecellV9e japb_pclkin-portsportendpointout-ports port@0Vendpointwport@1Vendpointcti@6b21000 2arm,coresight-ctiarm,primecellV9e japb_pclktpdm@6b48000"2qcom,coresight-tpdmarm,primecellV9e japb_pclk  out-portsportendpointocti@6c13000 2arm,coresight-ctiarm,primecellV09e japb_pclkfailcti@6c20000 2arm,coresight-ctiarm,primecellV9e japb_pclk disabledtpdm@6c28000"2qcom,coresight-tpdmarm,primecellV€9e japb_pclk  out-portsportendpointgcti@6c29000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@6c2a000 2arm,coresight-ctiarm,primecellV 9e japb_pclkcti@7020000 2arm,coresight-ctiarm,primecellV9e japb_pclketm@70400002arm,primecellV9e japb_pclkout-portsportendpointcti@7120000 2arm,coresight-ctiarm,primecellV9e japb_pclketm@71400002arm,primecellV9e japb_pclkout-portsportendpointcti@7220000 2arm,coresight-ctiarm,primecellV"9e japb_pclketm@72400002arm,primecellV$9e japb_pclkout-portsportendpointcti@7320000 2arm,coresight-ctiarm,primecellV29e japb_pclketm@73400002arm,primecellV49e japb_pclkout-portsportendpointcti@7420000 2arm,coresight-ctiarm,primecellVB9e japb_pclketm@74400002arm,primecellVD9e japb_pclkout-portsportendpointcti@7520000 2arm,coresight-ctiarm,primecellVR9e japb_pclketm@75400002arm,primecellVT9e japb_pclkout-portsportendpointcti@7620000 2arm,coresight-ctiarm,primecellVb9e japb_pclketm@76400002arm,primecellVd9e japb_pclkout-portsportendpointcti@7720000 2arm,coresight-ctiarm,primecellVr9e japb_pclketm@77400002arm,primecellVt9e japb_pclkout-portsportendpointfunnel@7800000+2arm,coresight-dynamic-funnelarm,primecellV9e japb_pclkin-ports port@0Vendpointport@1Vendpointport@2Vendpointport@3Vendpointport@4Vendpointport@5Vendpointport@6Vendpointport@7Vendpointout-portsportendpointfunnel@7810000+2arm,coresight-dynamic-funnelarm,primecellV9e japb_pclkin-ports port@0Vendpointport@2Vendpointport@3Vendpointport@4Vendpointport@5Vendpointout-portsportendpointytpdm@7830000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke@{ out-portsportendpointtpda@7832000"2qcom,coresight-tpdaarm,primecellV 9e japb_pclkin-portsportendpointout-portsportendpointtpdm@7860000"2qcom,coresight-tpdmarm,primecellV9e japb_pclk  out-portsportendpointtpda@7862000"2qcom,coresight-tpdaarm,primecellV 9e japb_pclkin-portsportendpointout-portsportendpointtpdm@78a0000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke { out-portsportendpointtpdm@78b0000"2qcom,coresight-tpdmarm,primecellV9e japb_pclke { out-portsportendpointtpda@78c0000"2qcom,coresight-tpdaarm,primecellV9e japb_pclkin-portsportendpointout-portsportendpointtpda@78d0000"2qcom,coresight-tpdaarm,primecellV9e japb_pclkin-portsportendpointout-portsportendpointcti@78e0000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@78f0000 2arm,coresight-ctiarm,primecellV9e japb_pclkcti@7900000 2arm,coresight-ctiarm,primecellV9e japb_pclkpmu@90b6300(2qcom,qcs615-cpu-bwmonqcom,sdm845-bwmonV c OE22 }opp-table2operating-points-v2opp-0opp-1Ȁpmu@90cd000.2qcom,qcs615-llcc-bwmonqcom,sc7280-llcc-bwmonV  O11}opp-table2operating-points-v2opp-0 5opp-1Oopp-2opp-3!fopp-4)opp-5.opp-6>opp-7Ropp-8^mmc@8804000$2qcom,qcs615-sdhciqcom,sdhci-msm-v5V@EhcOZhc_irqpwr_irq9,p,q*jifacecorexoh-} /v,00 123sdhc-ddrcpu-sdhcd,ɀhokaydefaultsleep _ckw7opp-table2operating-points-v2opp-50000000opp-100000000opp-202000000 F interconnect@9160000V 22qcom,qcs615-dc-nocsystem-cache-controller@92000002qcom,qcs615-llcc V  `Ellcc0_basellcc_broadcast_baseinterconnect@9680000V h2qcom,qcs615-gem-noc2interrupt-controller@b2200002qcom,qcs615-pdcqcom,pdc V "d$^^a}?dpower-management@c300000#2qcom,qcs615-aoss-qmpqcom,aoss-qmpV 0 Oesram@c3f00002qcom,rpmh-statsV ?iommu@15000000/2qcom,qcs615-smmu-500qcom,smmu-500arm,mmu-500V( OA^_`abcdefghijklmnopqrstuv;<=>?@ABCDEFGHIJKLMNOPQRSTU/spmi@c4400002qcom,spmi-pmic-arbPV D ``p @`Ecorechnlsobsrvrintrcnfg ;d Zperiph_irq Ozpmic@02qcom,pm8150qcom,spmi-pmicV pon@8002qcom,pm8998-ponVpwrkey2qcom,pm8941-pwrkeyO\= Ietokayresin2qcom,pm8941-resinO\= Iokayertemp-alarm@24002qcom,spmi-temp-alarmV$O$p|thermaladc@31002qcom,spmi-adc5V1 O1channel@0Vref_gndchannel@1V vref_1p25channel@6V die_tempadc-tm@35002qcom,spmi-adc-tm5V5O5  disabledrtc@60002qcom,pm8941-rtcV`a ErtcalarmOagpio@c000 2qcom,pm8150-gpioqcom,spmi-gpioV usb2-en-stategpio10$normalpmic@12qcom,pm8150qcom,spmi-pmicV interrupt-controller@17a00000 2arm,gic-v3 V O mailbox@17c0000002qcom,qcs615-apss-sharedqcom,sdm845-apss-sharedVwatchdog@17c10000#2qcom,apss-wdt-qcs615qcom,kpss-wdtV O9+timer@17c200002arm,armv7-timer-memV  frame@17c21000V Oframe@17c23000V0 O  disabledframe@17c25000VP O  disabledframe@17c27000Vp O  disabledframe@17c29000V O  disabledframe@17c2b000V° O  disabledframe@17c2d000V O disabledrsc@182000002qcom,rpmh-rsc0V !"Edrv-0drv-1drv-2$O,8  H apps_rsch!bcm-voter2qcom,bcm-voterclock-controller2qcom,qcs615-rpmh-clkjxo9*power-controller2qcom,qcs615-rpmhpd}-opp-table2operating-points-v2opp-0Xopp-1X0opp-2X@opp-3Xopp-4X8opp-5X opp-6X@opp-7XPopp-8Xopp-9Xregulators-02qcom,pm8150-rpmh-regulatorsbasmps3 ovreg_s3a~ ' smps4 ovreg_s4a~w@7smps5 ovreg_s5a~@ smps6 ovreg_s6a~l`ldo1 ovreg_l1a~r@ ldo2 ovreg_l2a~-P/M`ldo3 ovreg_l3a~B@ ldo5 ovreg_l5a~ Yaldo7 ovreg_l7a~w@ldo8 ovreg_l8a~0pldo10 ovreg_l10a~-p2ldo11 ovreg_l11a~̀9ldo12 ovreg_l12a~w@bldo13 ovreg_l13a~-1I0ldo15 ovreg_l15a~w@ ldo16 ovreg_l16a~-2ldo17 ovreg_l17a~-p26phy@88e20002qcom,qcs615-qusb2-phyV 9,* jcfg_ahbrefv,Ookayajb phy@88e30002qcom,qcs615-qusb2-phyV09,* jcfg_ahbrefv,Ookayajb phy@88e60002qcom,qcs615-qmp-usb3-phyV` 9,,,,jauxrefcfg_ahbpipev, , phyphy_phy"D0usb3_phy_pipe_clk_srcOokayZajbusb@a6f88002qcom,qcs615-dwc3qcom,dwc3V o09,,, ,,,&jcfg_noccoreifacesleepmock_utmixoC,,S$ D;d dd<Zpwr_evenths_phy_irqdp_hs_phy_irqdm_hs_phy_irqss_phy_irqh, v, okayusb@a600000 2snps,dwc3V ` /@ Ousb2-phyusb3-phyh  !peripheralusb@a8f88002qcom,qcs615-dwc3qcom,dwc3V 09,,, ,,,&jcfg_noccoreifacesleepmock_utmixoC,,S$ 8;d d 1Zpwr_evenths_phy_irqdp_hs_phy_irqdm_hs_phy_irqh, v,  ) okayusb@a800000 2snps,dwc3V  / O usb2-phy Fhigh-speed !hosttimer2arm,armv8-timer0Othermal-zonespm8150-thermal Td jtripstrip0 zs Epassivetrip1 z8 Ehottrip2 z6h  Ecriticalaliases /soc@0/mmc@7c4000 /soc@0/mmc@8804000$ /soc@0/geniqup@8c0000/serial@880000chosen serial0:115200n8clockssleep-clk 2fixed-clock }+xo-board-clk 2fixed-clock Iregulator-usb2-vbus2regulator-fixed oUSB2_VBUS default   interrupt-parent#address-cells#size-cellsmodelcompatiblechassis-typedevice_typeregenable-methodpower-domainspower-domain-namescapacity-dmips-mhzdynamic-power-coefficientnext-level-cache#cooling-cellsphandlecache-levelcache-unifiedcpuremote-endpointentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stopqcom,dload-mode#interconnect-cellsqcom,bcm-votersopp-sharedopp-hzrequired-opps#power-domain-cellsdomain-idle-statesrangesno-maphwlocksdma-ranges#clock-cells#reset-cellsclocksbitsreg-namesinterruptsinterrupt-namesclock-namesresetsoperating-points-v2iommusinterconnectsinterconnect-namesqcom,dll-configqcom,ddr-configsupports-cqedma-coherentstatuspinctrl-0pinctrl-1pinctrl-namesbus-widthmmc-ddr-1_8vmmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobevmmc-supplyvqmmc-supplynon-removableno-sdno-sdio#dma-cellsdma-channelsdma-channel-maskdmasdma-namesreset-nameslanes-per-directionphysphy-namesreset-gpiosvcc-supplyvcc-max-microampvccq2-supplyvccq2-max-microamp#phy-cellsvdda-phy-supplyvdda-pll-supplyqcom,eeqcom,controlled-remotelynum-channelsqcom,num-ees#hwlock-cellsgpio-rangesgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellswakeup-parentpinsfunctionbias-disabledrive-strengthbias-pull-upbias-pull-downqcom,cmb-element-bitsqcom,cmb-msrs-numqcom,dsb-element-bitsqcom,dsb-msrs-numarm,coresight-loses-context-with-cpuqcom,skip-power-upopp-peak-kBpscd-gpiosqcom,pdc-rangesmboxes#iommu-cells#global-interruptsinterrupts-extendedqcom,channeldebouncelinux,codeio-channelsio-channel-names#thermal-sensor-cells#io-channel-cellsqcom,pre-scalinglabeloutput-enablepower-source#redistributor-regionsredistributor-stride#mbox-cellsframe-numberqcom,drv-idqcom,tcs-offsetqcom,tcs-configopp-levelqcom,pmic-idregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-allow-set-loadregulator-allowed-modesnvmem-cellsvdd-supplyvdda-phy-dpdm-supplyqcom,tcsr-regclock-output-namesassigned-clocksassigned-clock-ratessnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirksnps,dis_enblslpm_quirksnps,has-lpm-erratumsnps,hird-thresholdsnps,usb3_lpm_capabledr_modeqcom,select-utmi-as-pipe-clkmaximum-speedpolling-delay-passivethermal-sensorstemperaturehysteresismmc0mmc1serial0stdout-pathclock-frequencygpioenable-active-highregulator-always-on