m80( =;tsd,px30-pp1516-ltk050h3148wtsd,px30-pp1516rockchip,px30 +47Theobroma Systems PP-1516 with LTK050H3148W Displayaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35psciZ cpu@2cpuarm,cortex-a35psciZ cpu@3cpuarm,cortex-a35psciZ idle-statespscicpu-sleeparm,idle-state"3Jx[k cluster-sleeparm,idle-state"3J[k opp-table-0operating-points-v2| opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal*8J tripstrip-point-0Zpfpassivetrip-point-1ZLfpassive soc-critZ8f criticalcooling-mapsmap0q vgpu-thermald*J tripsgpu-thresholdZpfpassivegpu-targetZLfpassive gpu-critZ8f criticalcooling-mapsmap0q vxin24m fixed-clockn6xin24m ypower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+ {power-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+ io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&baudclkapb_pclk ''%txrx/9Fdefault T()* disabledi2s@ff060000rockchip,px30-i2s-tdm  mclk_txmclk_rxhclk ''%txrx^+k rtx-mrx-mFdefault0T,-./01234567~ disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk ''%txrxFdefaultT89:;~ disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk ''%txrxFdefaultT<=>?~ disabledinterrupt-controller@ff131000 arm,gic-400@ @ `    syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+ +io-domains rockchip,px30-io-voltage-domainokay@AB%%Clvdsrockchip,px30-lvds Ddphy^+lvds disabledports+port@0+endpoint@0(E endpoint@1(F port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk ''%txrx/9Fdefault TGHI disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk ''%txrx/9FdefaultTJ disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk ''%txrx/9Fdefault TKLM disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk '' %txrx/9Fdefault TNOP disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk ' ' %txrx/9FdefaultTQokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk FdefaultTR+okaytouchscreen@14 goodix,gt9118S T FTFdefaultTUV PT \%pmic@20rockchip,rk809 xin32k TFdefaultTWiXXXX%%%XregulatorsDCDC_REG1vdd_log$~<pTq regulator-state-memi~DCDC_REG2vdd_arm$~<pTq regulator-state-mem~DCDC_REG3vcc_ddrregulator-state-memiDCDC_REG4 vcc_3v0_1v8$-<- Cregulator-state-memi-DCDC_REG5vcc_3v3$2Z<2Z %regulator-state-memi2ZLDO_REG2vcc_1v8$w@<w@ Bregulator-state-memiw@LDO_REG3vcc_1v0$B@<B@regulator-state-memiB@LDO_REG4vcc_2v8$*<* Sregulator-state-mem*LDO_REG5 vccio_sd$-<- Aregulator-state-memi-LDO_REG6 vcc_sdio$w@<w@ @regulator-state-memiw@LDO_REG7vcc_lcd$B@<B@regulator-state-memB@LDO_REG8 vcc_1v8_lcd$w@<w@regulator-state-memiw@LDO_REG9 vcca_1v8$w@<w@regulator-state-memw@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk FdefaultTY+okayi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  FdefaultTZ+okayfocus@cdongwoon,dw9714 [ aaccel@15memsic,mxc4005 \ FdefaultT]camera@36 ovti,ov5675644$^_` aFdefaultTbc P\"portendpoint(d+6t i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  FdefaultTe+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk ' ' %txrxGFdefaultTfghi+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk ''%txrxGFdefaultTjklmn+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkFdefaultToNokay pwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkFdefaultTpNokay pwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkFdefaultTqN disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkFdefaultTrN disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkFdefaultTsN disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkFdefaultTtN disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkFdefaultTuN disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkFdefaultTvN disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerdma-controller@ff240000arm,pl330arm,primecell$@Y apb_pclkp 'tsadc@ff280000rockchip,px30-tsadc( $,P,Xtsadcapb_pclkk rtsadc-apb^+{FinitdefaultsleepTwxwokay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-Wsaradcapb_pclkk rsaradc-apbokayBnvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphykrphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ y& xin24mgpll^+8@IFq рр  clock-controller@ff2bc000rockchip,px30-pmucru+yxin24m^+&&& G &syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & phyclkz usb480m_phyokay zhost-port D linestateokay }otg-port$BA@otg-bvalidotg-idlinestateokay |phy@ff2e0000rockchip,px30-dsi-dphy.& E refpclkk>rapb{ okay Dphy@ff2f0000rockchip,px30-csi-dphy/@Fpclk{ k/rapb^+okay usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otg ,peripheral4FU@  | usb2-phy{okayusb@ff340000 generic-ehci4 < }usb{okayusb@ff350000 generic-ohci5 = }usb{okayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed^+drmiiFdefaultT~{ k^ rstmmaceth disabledmdiosnps,dwmac-mdio+mmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-samplemwрFdefaultT{ disabledmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-samplemwрFdefault T{  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-samplemwрFdefault T{ okay%Cspi@ff3a0000 rockchip,sfc:@ 8:clk_sfchclk_sfc TFdefault{  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97ahbnfc7рFdefault T{  disabledopp-table-1operating-points-v2 opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuI{okay video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu aclkhclk{ iommu@ff442800rockchip,iommuD( Q aclkiface{  dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KDpclk Ddphy{ k=rapb^++okayports+port@0+endpoint@0( endpoint@1( port@1endpoint( panel@0leadtek,ltk050h3148wBFdefaultT PT  Sportendpoint( vop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vopk345 raxiahbdclk{ okayport+ endpoint@0( endpoint@1( Eiommu@ff460f00rockchip,iommuF M aclkiface{ okay vop@ff470000rockchip,px30-vop-litG Naclk_vopdclk_vophclk_vopk789 raxiahbdclk{  disabledport+ endpoint@0( endpoint@1( Fiommu@ff470f00rockchip,iommuG N aclkiface{  disabled isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_ispaclkhclkpclk dphy{ okayports+port@0endpoint+( diommu@ff4a8000rockchip,iommuJ F aclkiface{ okay qos@ff518000rockchip,px30-qossysconQ  qos@ff520000rockchip,px30-qossysconR  $qos@ff52c000rockchip,px30-qossysconR  qos@ff538000rockchip,px30-qossysconS  qos@ff538080rockchip,px30-qossysconS  qos@ff538100rockchip,px30-qossysconS  qos@ff538180rockchip,px30-qossysconS  qos@ff540000rockchip,px30-qossysconT  qos@ff540080rockchip,px30-qossysconT  qos@ff548000rockchip,px30-qossysconT  qos@ff548080rockchip,px30-qossysconT  qos@ff548100rockchip,px30-qossysconT  !qos@ff548180rockchip,px30-qossysconT  "qos@ff548200rockchip,px30-qossysconT  #qos@ff550000rockchip,px30-qossysconU  qos@ff550080rockchip,px30-qossysconU  qos@ff550100rockchip,px30-qossysconU  qos@ff550180rockchip,px30-qossysconU  qos@ff558000rockchip,px30-qossysconU  qos@ff558080rockchip,px30-qossysconU  pinctrlrockchip,px30-pinctrl^+1+>gpio@ff040000rockchip,gpio-bank &EU Tgpio@ff250000rockchip,gpio-bank% \EU gpio@ff260000rockchip,gpio-bank& ]EU \gpio@ff270000rockchip,gpio-bank' ^EU pcfg-pull-upa pcfg-pull-downn pcfg-pull-none} pcfg-pull-none-2ma}pcfg-pull-up-2maapcfg-pull-up-4maa pcfg-pull-none-4ma}pcfg-pull-down-4manpcfg-pull-none-8ma} pcfg-pull-up-8maa pcfg-pull-none-12ma}  pcfg-pull-up-12maa  pcfg-pull-none-smt} pcfg-output-highpcfg-output-lowpcfg-input-higha pcfg-inputi2c0i2c0-xfer   Ri2c1i2c1-xfer  Yi2c2i2c2-xfer  Zi2c3i2c3-xfer    etsadctsadc-otp-pin wtsadc-otp-out xuart0uart0-xfer    (uart0-cts  )uart0-rts  *uart1uart1-xfer  Guart1-cts Huart1-rts Iuart2-m0uart2m0-xfer  Juart2-m1uart2m1-xfer  uart3-m0uart3m0-xfer uart3m0-ctsuart3m0-rtsuart3-m1uart3m1-xfer  Kuart3m1-cts  Luart3m1-rts  Muart4uart4-xfer  Nuart4-cts Ouart4-rts Puart5uart5-xfer  Quart5-ctsuart5-rtsspi0spi0-clk fspi0-csn gspi0-miso  hspi0-mosi  ispi0-clk-hsspi0-miso-hs spi0-mosi-hs spi1spi1-clk jspi1-csn0  kspi1-csn1  lspi1-miso mspi1-mosi  nspi1-clk-hsspi1-miso-hsspi1-mosi-hs pdmpdm-clk0m0pdm-clk0m1pdm-clk1pdm-sdi0m0pdm-sdi0m1pdm-sdi1pdm-sdi2pdm-sdi3pdm-clk0m0-sleeppdm-clk0m1-sleeppdm-clk1-sleeppdm-sdi0m0-sleeppdm-sdi0m1-sleeppdm-sdi1-sleeppdm-sdi2-sleeppdm-sdi3-sleepi2s0i2s0-8ch-mclki2s0-8ch-sclktx ,i2s0-8ch-sclkrx  -i2s0-8ch-lrcktx .i2s0-8ch-lrckrx  /i2s0-8ch-sdo0 0i2s0-8ch-sdo1 2i2s0-8ch-sdo2 4i2s0-8ch-sdo3 6i2s0-8ch-sdi0 1i2s0-8ch-sdi1  3i2s0-8ch-sdi2  5i2s0-8ch-sdi3 7i2s1i2s1-2ch-mclki2s1-2ch-sclk 8i2s1-2ch-lrck 9i2s1-2ch-sdi :i2s1-2ch-sdo ;i2s2i2s2-2ch-mclki2s2-2ch-sclk <i2s2-2ch-lrck =i2s2-2ch-sdi >i2s2-2ch-sdo ?sdmmcsdmmc-clk sdmmc-cmd sdmmc-det sdmmc-bus1sdmmc-bus4@ sdiosdio-clk sdio-cmd sdio-bus4@ emmcemmc-clk  emmc-cmd  emmc-rstnout emmc-bus1emmc-bus4@emmc-bus8 emmc-reset  flashflash-cs0 flash-rdy  flash-dqs  flash-ale  flash-cle  flash-wrn  flash-cslflash-rdn flash-bus8 sfcsfc-bus4@ sfc-bus2 sfc-cs0 sfc-clk  lcdclcdc-rgb-dclk-pinlcdc-rgb-m0-hsync-pinlcdc-rgb-m0-vsync-pinlcdc-rgb-m0-den-pinlcdc-rgb888-m0-data-pins     lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins     lcdc-rgb888-m1-data-pins   lcdc-rgb666-m1-data-pins   lcdc-rgb565-m1-data-pins   pwm0pwm0-pin opwm1pwm1-pin ppwm2pwm2-pin  qpwm3pwm3-pin rpwm4pwm4-pin spwm5pwm5-pin tpwm6pwm6-pin upwm7pwm7-pin vgmacrmii-pins  ~mac-refclk-12ma  mac-refclk cif-m0cif-clkout-m0  bdvp-d2d9-m0   dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1dvp-d2d9-m1  dvp-d0d1-m1 d10-d11-m1 ispisp-prelightaccelaccel-int  ]cameracam-afvdd-en  cam-avdd-en cam-dovdd-en cam-dvdd-en cam-pwdn cledsdebug-led-pin heartbeat-led-pin paneldsp-rst  tch-int Utch-rst  Vpmicpmic-int Wchosenserial5:115200n8backlightpwm-backlightXa beeper pwm-beeperemmc-pwrseqmmc-pwrseq-emmcTFdefault P  gpio-leds gpio-ledsFdefaultTled-0debug J noneled-1 heartbeat JT heartbeatregulator-vccsysregulator-fixed vcc5v0_sys$LK@<LK@ Xregulator-vcc-cam-avddregulator-fixed vcc_cam_avdd FdefaultT$*<* S ^regulator-vcc-cam-dovddregulator-fixedvcc_cam_dovdd FdefaultT$w@<w@ B `regulator-vcc-cam-dvddregulator-fixed vcc_cam_dvdd  *FdefaultT$O<O % _regulator-vcc-lens-afvddregulator-fixedvcc_lens_afvdd  FdefaultT$*<* S [ compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1mmc0device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointAVDD28-supplyirq-gpiosreset-gpiosVDDIO-supplysystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendvcc-supplyassigned-clocksassigned-clock-ratesavdd-supplydvdd-supplydovdd-supplylens-focusorientationrotationdata-laneslink-frequenciesnum-cs#pwm-cellsarm,pl330-periph-burst#dma-cellsrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modebus-widthfifo-depthmax-frequencycap-mmc-highspeedmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplymali-supplyiommus#iommu-cellsbacklightiovcc-supplyvci-supplyrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathpower-supplypwmslabellinux,default-triggergpiovin-supplyenable-active-high