8(Qh)rockchip,rk3562-evb2-v10rockchip,rk3562 +7Rockchip RK3562 EVB V20 Boardaliases=/pinctrl/gpio@ff260000C/pinctrl/gpio@ff620000I/pinctrl/gpio@ff630000O/pinctrl/gpio@ffac0000U/pinctrl/gpio@ffad0000clock-xin32k fixed-clock[hxxin32kclock-xin24m fixed-clock[hn6xxin24mcpus+cpu@0cpuarm,cortex-a53pscicpu@1cpuarm,cortex-a53pscicpu@2cpuarm,cortex-a53pscicpu@3cpuarm,cortex-a53psciidle-statespscicpu-sleeparm,idle-state#:xK[opp-table-cpu0operating-points-v2lopp-408000000wQ ~ 0@opp-600000000w#F ~ 0@opp-816000000w0, ~ 0@opp-1008000000w< ~ P P0@opp-1200000000wG ~HH0@opp-1416000000wTfr ~B@B@0@opp-1608000000w_" ~ԼԼ0@opp-1800000000wkI ~**0@opp-2016000000wx) ~000@opp-table-gpuoperating-points-v22opp-300000000w ~ B@opp-400000000wׄ ~ B@opp-500000000we ~ B@opp-600000000w#F ~ B@opp-700000000w)' ~ B@opp-800000000w/ ~~~B@opp-900000000w5 ~B@B@B@arm-pmuarm,cortex-a53-pmu0firmwarescmi arm,scmi-smc ނ+protocol@14[pinctrlrockchip,rk3562-pinctrl + gpio@ff260000rockchip,gpio-bank&    .:gpio@ff620000rockchip,gpio-bankb    .:gpio@ff630000rockchip,gpio-bankc   @  .:gpio@ffac0000rockchip,gpio-bank T & `  .:gpio@ffad0000rockchip,gpio-bank U '  .:]pcfg-pull-upKpcfg-pull-noneX pcfg-pull-none-drv-level-1Xepcfg-pull-none-drv-level-3Xepcfg-pull-none-drv-level-4Xepcfg-pull-up-drv-level-2Kepcfg-pull-none-smtXtpcfg-output-lowcamcan0can1clkclk0clk1cpudsmemmcethfspigpui2c0i2c0-xfer   i2c1i2c1m0-xfer   Ti2c2i2c2m0-xfer  Ui2c3i2c3m0-xfer Vi2c4i2c4m0-xfer Wi2c5i2c5m0-xfer Xi2s0i2s1i2s2ispjtagnpupcie20pdmpmicpmic-intpmupwm0pwm0m0-pins"pwm1pwm1m0-pins#pwm2pwm2m0-pins$pwm3pwm3m0-pins%pwm4pwm4m0-pins;pwm5pwm5m0-pins<pwm6pwm6m0-pins=pwm7pwm7m0-pins>pwm8pwm8m0-pins?pwm9pwm9m0-pins@pwm10pwm10m0-pins Apwm11pwm11m0-pinsBpwm12pwm12m0-pinsCpwm13pwm13m0-pinsDpwm14pwm14m0-pinsEpwm15pwm15m0-pinsFpwrrefrgmiirmiisdmmc0sdmmc0-bus4@   Jsdmmc0-clkKsdmmc0-cmdLsdmmc0-detMsdmmc1sdmmc1-bus4@Qsdmmc1-clkSsdmmc1-cmdRspdifspi0spi0m0-pins0!spi0m0-csn0spi0m0-csn1 spi1spi1m0-pins05spi1m0-csn03spi1m0-csn14spi2spi2m0-pins08spi2m0-csn0 6spi2m0-csn1 7tsadcuart0uart1uart1m0-xfer 9uart1m0-ctsn :uart2uart3uart4uart5uart6uart7uart8uart9vosdio-pwrseqwifi-enable-h [usbusb-host-pwren _usb-otg-pwren `psci arm,psci-1.0smcreserved-memory+shmem@10f000arm,scmi-shmem timerarm,armv8-timer0   soc simple-bus+pcie@fe000000*rockchip,rk3562-pcierockchip,rk3568-pcie0@Pdbiapbconfig(      $aclk_mstaclk_slvaclk_dbipclkauxpciHsyspmcmsglegacyerrmsi:` )6EO Tpcie-phy^T @l Mspipe+okay legacy-interrupt-controller:  interrupt-controller@fe901000 arm,gic-400:@ @ `   qos@fee03800rockchip,rk3562-qossyscon8 qos@fee10000rockchip,rk3562-qossyscon qos@fee10100rockchip,rk3562-qossyscon qos@fee10200rockchip,rk3562-qossyscon qos@fee10300rockchip,rk3562-qossyscon qos@fee10400rockchip,rk3562-qossyscon qos@fee20000rockchip,rk3562-qossyscon qos@fee30000rockchip,rk3562-qossyscon &qos@fee40000rockchip,rk3562-qossyscon 'qos@fee50000rockchip,rk3562-qossyscon (qos@fee60000rockchip,rk3562-qossyscon +qos@fee70000rockchip,rk3562-qossyscon )qos@fee70100rockchip,rk3562-qossyscon *qos@fee80000rockchip,rk3562-qossyscon ,qos@fee90000rockchip,rk3562-qossyscon /qos@fee90100rockchip,rk3562-qossyscon -qos@fee90200rockchip,rk3562-qossyscon .qos@feea0000rockchip,rk3562-qossyscon 0qos@feea0100rockchip,rk3562-qossyscon 1qos@feeb0000rockchip,rk3562-qossyscon qos@feeb0100rockchip,rk3562-qossyscon qos@feeb0200rockchip,rk3562-qossyscon qos@feeb0300rockchip,rk3562-qossyscon qos@feeb0400rockchip,rk3562-qossyscon qos@feeb0500rockchip,rk3562-qossyscon qos@feeb0600rockchip,rk3562-qossyscon qos@feeb0700rockchip,rk3562-qossyscon qos@feeb0800rockchip,rk3562-qossyscon syscon@ff010000*rockchip,rk3562-pmu-grfsysconsimple-mfdreboot-modesyscon-reboot-mode RBRBRBRB syscon@ff030000rockchip,rk3562-sys-grfsysconsyscon@ff040000 rockchip,rk3562-peri-grfsysconHsyscon@ff060000rockchip,rk3562-ioc-grfsyscon syscon@ff090000"rockchip,rk3562-usbphy-grfsyscon syscon@ff098000#rockchip,rk3562-pipephy-grfsyscon Iclock-controller@ff100000rockchip,rk3562-cru[    Fq;: i2c@ff200000(rockchip,rk3562-i2crockchip,rk3399-i2c  & % i2cpclk  default+okaypmic@20rockchip,rk809  -defaultpmic-sleeppmic-power-offpmic-reset)J[xrk808-clkout1rk808-clkout2Xdp|ZregulatorsDCDC_REG1 pq/ Fvdd_logicregulator-state-memUDCDC_REG2 pq/Fvdd_cpuregulator-state-memUDCDC_REG3/Fvcc_ddrregulator-state-memnDCDC_REG4 pq/Fvdd_gpuregulator-state-memULDO_REG1** Fvcc2v8_dvpregulator-state-memULDO_REG2   Fvdda_0v9regulator-state-memULDO_REG3   Fvdda0v9_pmuregulator-state-memn LDO_REG4-- Fvccio_acodecregulator-state-memULDO_REG5w@2Z Fvccio_sdOregulator-state-memULDO_REG62Z2Z Fvcc3v3_pmuregulator-state-memn2ZLDO_REG7w@w@ Fvcca_1v8regulator-state-memULDO_REG8w@w@ Fvcca1v8_pmuregulator-state-memnw@LDO_REG9w@w@ Fvcc1v8_dvpregulator-state-memUDCDC_REG5w@w@Fvcc_1v8Gregulator-state-memUSWITCH_REG1Fvcc_3v3regulator-state-memUSWITCH_REG2 Fvcc3v3_sdNregulator-state-memUserial@ff210000&rockchip,rk3562-uartsnps,dw-apb-uart!  + 'baudclkapb_pclkokayspi@ff220000(rockchip,rk3562-spirockchip,rk3066-spi" 4 - ,spiclkapb_pclk  txrxdefault  !+ disabledpwm@ff230000(rockchip,rk3562-pwmrockchip,rk3328-pwm# 0 / pwmpclkdefault" disabledpwm@ff230010(rockchip,rk3562-pwmrockchip,rk3328-pwm# 0 / pwmpclkdefault# disabledpwm@ff230020(rockchip,rk3562-pwmrockchip,rk3328-pwm#  0 / pwmpclkdefault$ disabledpwm@ff230030(rockchip,rk3562-pwmrockchip,rk3328-pwm#0 0 / pwmpclkdefault% disabledpower-management@ff258000&rockchip,rk3562-pmusysconsimple-mfd%power-controller!rockchip,rk3562-power-controller+power-domain@8&power-domain@7'power-domain@11 (power-domain@12 )*+power-domain@10 +power-domain@13 ,+power-domain@14 -./power-domain@1501gpu@ff320000&rockchip,rk3562-maliarm,mali-bifrost2@ k iclk_gpuclk_gpu_brgaclk_gpu4$LMK jobmmugpu2^ disabledspi@ff640000rockchip,rk3066-spid 5 spiclkapb_pclktxrxdefault 345+ disabledspi@ff650000rockchip,rk3066-spie 6 spiclkapb_pclktxrxdefault 678+ disabledserial@ff670000&rockchip,rk3562-uartsnps,dw-apb-uartg  baudclkapb_pclkokaydefault9:serial@ff680000&rockchip,rk3562-uartsnps,dw-apb-uarth   baudclkapb_pclk disabledserial@ff690000&rockchip,rk3562-uartsnps,dw-apb-uarti ! baudclkapb_pclk disabledserial@ff6a0000&rockchip,rk3562-uartsnps,dw-apb-uartj " baudclkapb_pclk disabledserial@ff6b0000&rockchip,rk3562-uartsnps,dw-apb-uartk # baudclkapb_pclk disabledserial@ff6c0000&rockchip,rk3562-uartsnps,dw-apb-uartl $ baudclkapb_pclk disabledserial@ff6d0000&rockchip,rk3562-uartsnps,dw-apb-uartm % baudclkapb_pclk disabledserial@ff6e0000&rockchip,rk3562-uartsnps,dw-apb-uartn & baudclkapb_pclk disabledserial@ff6f0000&rockchip,rk3562-uartsnps,dw-apb-uarto ' baudclkapb_pclk disabledpwm@ff700000(rockchip,rk3562-pwmrockchip,rk3328-pwmp  pwmpclkdefault; disabledpwm@ff700010(rockchip,rk3562-pwmrockchip,rk3328-pwmp  pwmpclkdefault< disabledpwm@ff700020(rockchip,rk3562-pwmrockchip,rk3328-pwmp   pwmpclkdefault= disabledpwm@ff700030(rockchip,rk3562-pwmrockchip,rk3328-pwmp0  pwmpclkdefault> disabledpwm@ff710000(rockchip,rk3562-pwmrockchip,rk3328-pwmq  pwmpclkdefault? disabledpwm@ff710010(rockchip,rk3562-pwmrockchip,rk3328-pwmq  pwmpclkdefault@ disabledpwm@ff710020(rockchip,rk3562-pwmrockchip,rk3328-pwmq   pwmpclkdefaultA disabledpwm@ff710030(rockchip,rk3562-pwmrockchip,rk3328-pwmq0  pwmpclkdefaultB disabledpwm@ff720000(rockchip,rk3562-pwmrockchip,rk3328-pwmr  pwmpclkdefaultC disabledpwm@ff720010(rockchip,rk3562-pwmrockchip,rk3328-pwmr  pwmpclkdefaultD disabledpwm@ff720020(rockchip,rk3562-pwmrockchip,rk3328-pwmr   pwmpclkdefaultE disabledpwm@ff720030(rockchip,rk3562-pwmrockchip,rk3328-pwmr0  pwmpclkdefaultF disabledadc@ff730000rockchip,rk3562-saradcs ( saradcapb_pclkl  ssaradc-apbokayGYphy@ff750000rockchip,rk3562-naneng-combphyu :  refapbpipe :l OsphyH0Iokayspi@ff860000 rockchip,sfc  clk_sfchclk_sfc+ disabledmmc@ff8700000rockchip,rk3562-dwcmshcrockchip,rk3588-dwcmshc ?  ( corebusaxiblocktimer(l scorebusaxiblocktimerF okayT^flzmmc@ff8800000rockchip,rk3562-dw-mshcrockchip,rk3288-dw-mshc 8 biuciuciu-driveciu-sampleF l sresetokay^TdefaultJKLM NOmmc@ff8900000rockchip,rk3562-dw-mshcrockchip,rk3288-dw-mshc 9 biuciuciu-driveciu-sampleF l sresetokayfT$1GPldefault QRSdma-controller@ff990000arm,pl330arm,primecell@R  apb_pclkonii2c@ffa00000(rockchip,rk3562-i2crockchip,rk3399-i2c  i2cpclk  defaultT+ disabledi2c@ffa10000(rockchip,rk3562-i2crockchip,rk3399-i2c !  i2cpclk defaultU+ disabledi2c@ffa20000(rockchip,rk3562-i2crockchip,rk3399-i2c "  i2cpclk defaultV+ disabledi2c@ffa30000(rockchip,rk3562-i2crockchip,rk3399-i2c #  i2cpclk defaultW+ disabledi2c@ffa40000(rockchip,rk3562-i2crockchip,rk3399-i2c $  i2cpclk defaultX+ disabledadc@ffaa0000rockchip,rk3562-saradc | D Vsaradcapb_pclkl  ssaradc-apb disabledchosentserial0:1500000n8adc-keys adc-keysYbuttonsw@dbutton-vol-ups volume upBhbutton-vol-downr volume downQ0button-menumenu 5button-backbackOleds gpio-ledsled-0   heartbeatsdio-pwrseqmmc-pwrseq-simpleZ ext_clockdefault[  Pregulator-vcc12v-dcinregulator-fixed Fvcc12v_dcin\regulator-vcc3v3-pcie20regulator-fixedFvcc3v3_pcie202Z2Z 0A\regulator-vcc5v0-sysregulator-fixed Fvcc5v0_sysLK@LK@A\aregulator-vcc5v0-usbregulator-fixed Fvcc5v0_usbLK@LK@A\^regulator-vcc5v0-usb-hostregulator-fixedFvcc5v0_usb_hostLK@LK@ L]A^default_regulator-vcc5v0-usb-otgregulator-fixedFvcc5v0_usb_otgLK@LK@ LA^default`regulator-vcc3v3-clkregulator-fixed Fvcc3v3_clk2Z2ZAaregulator-vcc-sysregulator-fixed Fvcc3v3_sys2Z2ZA\ compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4#clock-cellsclock-frequencyclock-output-namesdevice_typeregenable-methodclockscpu-idle-statesoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendopp-supported-hwinterruptsinterrupt-affinityshmemarm,smc-idrockchip,grfrangesgpio-controllergpio-rangesinterrupt-controller#gpio-cells#interrupt-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-lowrockchip,pinsno-mapreg-namesbus-rangeclock-namesinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speednum-ib-windowsnum-viewportnum-ob-windowsnum-lanesphysphy-namespower-domainsresetsreset-namesstatusreset-gpiosvpcie3v3-supplyoffsetmode-normalmode-loadermode-recoverymode-bootloader#reset-cellsassigned-clocksassigned-clock-ratespinctrl-namespinctrl-0rockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-initial-moderegulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltreg-shiftreg-io-widthdmasdma-namesnum-cs#pwm-cells#power-domain-cellspm_qos#io-channel-cellsvref-supply#phy-cellsrockchip,pipe-grfrockchip,pipe-phy-grfmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-strobefull-pwr-cycle-in-suspendfifo-depthno-mmccap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqarm,pl330-periph-burst#dma-cellsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallinux,codelabelpress-threshold-microvoltlinux,default-triggerpost-power-on-delay-msenable-active-highstartup-delay-usvin-supplygpio