8 (  6,bigtreetech,cb2-mantabigtreetech,cb2rockchip,rk35667BigTreeTech CB2aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000cpus cpu@0cpu,arm,cortex-a55psci%2@DQ^@p} cpu@100cpu,arm,cortex-a55psci%2@DQ^@p} cpu@200cpu,arm,cortex-a55psci%2@DQ^@p} cpu@300cpu,arm,cortex-a55psci%2@DQ^@p} l3-cache,cache'4@Fdisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smcՂ protocol@14hdmi-sound,simple-audio-cardHDMI i2s#=okaysimple-audio-card,codecDsimple-audio-card,cpuD pmu,arm,cortex-a55-pmu0NY psci ,arm,psci-1.0smcreserved-memory lshmem@10f000,arm,scmi-shmemstimer,arm,armv8-timer0N   zxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob N_ sata-phy =disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob N` sata-phy =disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Nref_clksuspend_clkbus_clkhost utmi_wide=okay usb2-phy8 ?high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Nref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide=okayinterrupt-controller@fd400000 ,arm,gic-v3 @F N MbsA}(l msi-controller@fd440000,arm,gic-v3-itsD]usb@fd800000 ,generic-ehci Nusb=okayusb@fd840000 ,generic-ohci Nusb=okayusb@fd880000 ,generic-ehci Nusb=okayusb@fd8c0000 ,generic-ohci Nusb=okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd[io-domains&,rockchip,rk3568-pmu-io-voltage-domain=okay"syscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru0clock-controller@fdd20000,rockchip,rk3568-cruxin24m0= MG byi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c N.- i2cpclkdefault =okayregulator@1c ,tcs,tcs4525vdd_cpu 45 "regulator-state-mem?pmic@20,rockchip,rk809 !N=HbmclkH-defaultpmic-sleeppmic-power-offpmic-reset"#Xi$$$$$$$$$regulatorsDCDC_REG1 pq vdd_logicregulator-state-mem?DCDC_REG2 pqvdd_gpuCregulator-state-mem?DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4 pqvdd_npuregulator-state-mem?LDO_REG1  vdda0v9_imageWregulator-state-mem?LDO_REG2   vdda_0v9regulator-state-mem?LDO_REG3   vdda0v9_pmuregulator-state-mem LDO_REG4-- vccio_acodecregulator-state-mem?LDO_REG5w@2Z vccio_sdregulator-state-mem?LDO_REG62Z2Z vcc3v3_pmuregulator-state-mem2ZLDO_REG7w@w@ vcca_1v8regulator-state-mem?LDO_REG8w@w@ vcca1v8_pmuregulator-state-memw@LDO_REG9w@w@vcca1v8_imageXregulator-state-mem?DCDC_REG5w@w@vcc_1v8regulator-state-mem?SWITCH_REG1vcc_3v3regulator-state-mem?SWITCH_REG2 vcc3v3_sdregulator-state-mem?codec/serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Nt ,baudclkapb_pclkL%%&defaultQ^ =disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'defaulth =disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(defaulth =disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)defaulth =disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk*defaulth =disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllers power-domain@7+spower-domain@8 ,-.spower-domain@9  /01spower-domain@10 234567spower-domain@11 8spower-domain@13 9spower-domain@14 :;<spower-domain@15=>?@Asgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$N()' jobmmugpugpubus=okayBCvideo-codec@fdea0400,rockchip,rk3568-vpu Nvdpu aclkhclkD iommu@fdea0800,rockchip,rk3568-iommu@ N aclkiface Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga NZaclkhclksclk&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu N@ aclkhclkE iommu@fdee0800,rockchip,rk3568-iommu@ N? aclkiface Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Nd biuciuciu-driveciu-sampleрreset =disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aN macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmacethyFGH*=okay=bMsY@3input@I Krgmii-iddefaultJKLMNOmdio,snps,dwmac-mdio phy@0,ethernet-phy-ieee802.3-c22TN  c!oIstmmac-axi-configFrx-queues-configGqueue0tx-queues-configHqueue0vop@fe040000 0@vopgamma-lut N(%aclkhclkdclk_vp0dclk_vp1dclk_vp2P y=okay,rockchip,rk3566-vop=bports port@0 endpoint@2QYport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? N aclkiface =okayPdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi NDpclkdphyR apby =disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi NEpclkdphyS apby =disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  N-((iahbisfrcecrefdefault TUV QyX=okayWXports port@0endpointYQport@1endpointZqos@fe128000,rockchip,rk3568-qossyscon +qos@fe138080,rockchip,rk3568-qossyscon :qos@fe138100,rockchip,rk3568-qossyscon ;qos@fe138180,rockchip,rk3568-qossyscon <qos@fe148000,rockchip,rk3568-qossyscon ,qos@fe148080,rockchip,rk3568-qossyscon -qos@fe148100,rockchip,rk3568-qossyscon .qos@fe150000,rockchip,rk3568-qossyscon 8qos@fe158000,rockchip,rk3568-qossyscon 2qos@fe158100,rockchip,rk3568-qossyscon 3qos@fe158180,rockchip,rk3568-qossyscon 4qos@fe158200,rockchip,rk3568-qossyscon 5qos@fe158280,rockchip,rk3568-qossyscon 6qos@fe158300,rockchip,rk3568-qossyscon 7qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon =qos@fe190280,rockchip,rk3568-qossyscon >qos@fe190300,rockchip,rk3568-qossyscon ?qos@fe190380,rockchip,rk3568-qossyscon @qos@fe190400,rockchip,rk3568-qossyscon Aqos@fe198000,rockchip,rk3568-qossyscon 9qos@fe1a8000,rockchip,rk3568-qossyscon /qos@fe1a8080,rockchip,rk3568-qossyscon 0qos@fe1a8100,rockchip,rk3568-qossyscon 1dfi@fe230000,rockchip,rk3568-dfi# N [pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<NKJIHGsyspmcmsglegacyerr ($aclk_mstaclk_slvaclk_dbipclkauxpcib*`=\\\\K\kz] pcie-phyTl @@pipe =okaydefault^ c_ `legacy-interrupt-controllerbM NH\mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Nb biuciuciu-driveciu-sampleрreset=okaydefaultabcdemmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Nc biuciuciu-driveciu-sampleрreset=okay   f *default ghi 8Zwifi@1,brcm,bcm4329-fmacjN  host-wakedefaultk V spi@fe300000 ,rockchip,sfc0@ Nexvclk_sfchclk_sfcldefault=okay mmc@fe310000,rockchip,rk3568-dwcmshc1 N={}M n6(|zy{}corebusaxiblocktimer=okay  *default mnorng@fe388000,rockchip,rk3568-rng8@po coreahbm =disabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ N4==AMFqFq?C9mclk_txmclk_rxhclkLp jtxPQ tx-mrx-myX=okay i2s@fe410000,rockchip,rk3568-i2s-tdmA N5=EIMFqFqGK:mclk_txmclk_rxhclkLpp jrxtxRS tx-mrx-mydefaultqrstX=okay ti2s@fe420000,rockchip,rk3568-i2s-tdmB N6=MMFqOO;mclk_txmclk_rxhclkLpp jtxrxTtx-mydefaultuvwxX =disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC N7SW<mclk_txmclk_rxhclkLpp jtxrxUV tx-mrx-myX =disabledpdm@fe440000,rockchip,rk3568-pdmD NLZYpdm_clkpdm_hclkLp  jrxyz{|}~defaultXpdm-mX =disabledspdif@fe460000,rockchip,rk3568-spdifF Nf mclkhclk_\Lp jtxdefaultX =disableddma-controller@fe530000,arm,pl330arm,primecellS@N    apb_pclk %dma-controller@fe550000,arm,pl330arm,primecellU@N   apb_pclk pi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ N/HG i2cpclkdefault  =disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ N0JI i2cpclkdefault  =disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ N1LK i2cpclkdefault =okaytouchscreen@48 ,ti,tsc2007H=okay    i2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] N2NM i2cpclkdefault  =disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ N3PO i2cpclkdefault  =disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` N tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia NgRQspiclkapb_pclkL%% jtxrxdefault   =disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib NhTSspiclkapb_pclkL%% jtxrxdefault  =disabledcan@0,microchip,mcp2515Ndefault  $ $spi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic NiVUspiclkapb_pclkL%% jtxrxdefault   =disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid NjXWspiclkapb_pclkL%% jtxrxdefault  =disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Nubaudclkapb_pclkL%% defaultQ^=okay jtxrx bluetooth,brcm,bcm4345c5lpo j -j ?jdefault  N$ Zserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Nv# baudclkapb_pclkL%%defaultQ^=okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Nw'$baudclkapb_pclkL%%defaultQ^ =disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Nx+(baudclkapb_pclkL%% defaultQ^ =disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Ny/,baudclkapb_pclkL% % defaultQ^ =disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Nz30baudclkapb_pclkL% % defaultQ^ =disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk N{74baudclkapb_pclkL%%defaultQ^ =disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl N|;8baudclkapb_pclkL%%defaultQ^ =disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm N}?<baudclkapb_pclkL%%defaultQ^ =disabledthermal-zonescpu-thermal gd } tripscpu_alert0 p passivecpu_alert1 $ passivecpu_crit s  criticalcooling-mapsmap0 0 gpu-thermal g } tripsgpu-threshold p passivegpu-target $ passivegpu-crit s  criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq Ns=Mf@ `tsadcapb_pclky sdefaultsleep  =okaysaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr N]saradcapb_pclk saradc-apb =okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaulth =disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaulth =disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaulth =disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaulth =disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaulth =disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaulth =disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaulth =disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaulth =disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaulth =disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaulth =disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaulth =disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaulth =disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe="Mphy  - C=okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe=%Mphy  - C=okayphy@fe870000,rockchip,rk3568-csi-dphyypclk Capby =disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz C apb =disabledRmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ C apb =disabledSusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m N N=okayhost-port C=okay ^otg-port C=okay ^usb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m N N=okayhost-port C=okay ^otg-port C=okay ^pinctrl,rockchip,rk3568-pinctrly[ lgpio@fdd60000,rockchip,gpio-bank N!.  i y  Mb!gpio@fe740000,rockchip,gpio-bankt N"cd i y  Mb_gpio@fe750000,rockchip,gpio-banku N#ef i y@  Mbjgpio@fe760000,rockchip,gpio-bankv N$gh i y`  Mbgpio@fe770000,rockchip,gpio-bankw N%ij i y  Mbpcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-1  [pcfg-pull-none-drv-level-2  [pcfg-pull-none-drv-level-3  [pcfg-pull-up-drv-level-1  [pcfg-pull-up-drv-level-2  [pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   memmc-clk nemmc-cmd oeth0eth1flashfspifspi-pins` lgmac0gmac1gmac1m0-miim Jgmac1m0-clkinout Ngmac1m0-rx-bus20    Lgmac1m0-tx-bus20  Kgmac1m0-rgmii-clk Mgmac1m0-rgmii-bus@ Ogpuhdmitxhdmitxm0-cec Vhdmitx-scl Thdmitx-sda Ui2c0i2c0-xfer  i2c1i2c1-xfer  i2c2i2c2m1-xfer   i2c3i2c3m0-xfer i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrcktx ri2s1m0-mclk #i2s1m0-sclktx qi2s1m0-sdi0  si2s1m0-sdo0 ti2s2i2s2m0-lrcktx vi2s2m0-sclktx ui2s2m0-sdi wi2s2m0-sdo xi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ypdmm0-clk1 zpdmm0-sdi0  {pdmm0-sdi1  |pdmm0-sdi2  }pdmm0-sdi3 ~pmicpmic-int "pmupwm0pwm0m1-pins 'pwm1pwm1m0-pins (pwm2pwm2m0-pins )pwm3pwm3-pins *pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m1-pins pwm13pwm13m1-pins pwm14pwm14m1-pins pwm15pwm15m1-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ asdmmc0-clk bsdmmc0-cmd csdmmc0-det dsdmmc1sdmmc1-bus4@ gsdmmc1-clk isdmmc1-cmd hsdmmc2spdifspdifm0-tx spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m1-pins0 spi3m1-cs0 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer &uart1uart1m0-xfer   uart1m0-ctsn uart1m0-rtsn  uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m1-xfer uart6uart6m0-xfer uart7uart7m2-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2btbt-enable-h bt-host-wake-l bt-wake-l pciepcie-drv  pcie-reset-h  ^sdio-pwrseqwifi-enable-h wifi-host-wake-l  kusbvcc5v0-host-en vcc5v0-otg-en vcc5v0-usb2t-en vcc5v0-usb2b-en work-ledled-heartbeat led-blue mcp2515mcp2515-int-pin opp-table-0,operating-points-v2 opp-408000000 Q P P0 @opp-600000000 #F P P0 @opp-816000000 0, P P0 @ opp-1104000000 Aʹ 0 @opp-1416000000 Tfr 0 @opp-1608000000 _" 0 @opp-1800000000 kI 000 @opp-table-1,operating-points-v2Bopp-200000000  P PB@opp-300000000  P PB@opp-400000000 ׄ P PB@opp-600000000 #F B@opp-700000000 )' ~~B@opp-800000000 / B@B@B@chosen serial2:1500000n8clock-25000000-cam ,fixed-clock}x@ ext_cam_clkclock-8000000-mcp2515 ,fixed-clockzhdmi-con,hdmi-connectoraportendpointZleds ,gpio-ledsled-0 & ,power i 5default-ondefaultled-1 & ,heartbeat i! 5heartbeatdefaultpwm-fan,pwm-fan K2d ZPrk809-sound,simple-audio-card i2s Analog RK809#simple-audio-card,cpuDsimple-audio-card,codecDsdio-pwrseq,mmc-pwrseq-simple ext_clockdefault _ c!fregulator-vbus,regulator-fixedvbusLK@LK@regulator-vcc12v-dcin,regulator-fixed vcc12v_dcinregulator-vcc3v3-pcie,regulator-fixed vcc3v3_pcie v i! default2Z2Z`regulator-vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z$regulator-vcc5v0-host,regulator-fixed v i!default vcc5v0_host3LK@LK@regulator-vcc5v0-otg,regulator-fixed v i! default vcc5v0_otg3LK@LK@regulator-vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@ regulator-vcc5v0-usb,regulator-fixed vcc5v0_usbLK@LK@regulator-vcc5v0-usb2b,regulator-fixed v !default vcc5v0_usb2bLK@LK@regulator-vcc5v0-usb2t,regulator-fixed v i!default vcc5v0_usb2tLK@LK@regulator-vcc-5v,regulator-fixedvcc_5vLK@LK@regulator-vcc-sd,regulator-fixed2Z2Zvcc_sd$e interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-ramp-delayregulator-boot-onregulator-always-onvin-supplyfcs,suspend-voltage-selectorregulator-off-in-suspend#sound-dai-cellssystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-on-in-suspendregulator-suspend-microvoltrockchip,mic-in-differentialdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modereset-delay-usreset-gpiosreset-post-delay-ussnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablerockchip,default-sample-phasebrcm,drive-strengthdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsti,x-plate-ohmsti,rt-thrti,fuzzxti,fuzzyspi-max-frequencyvdd-supplyxceiver-supplyuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disableinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolorfunctionlinux,default-triggercooling-levelspwmspost-power-on-delay-msenable-active-highgpio