8(  ',friendlyarm,nanopi-r3srockchip,rk35667FriendlyElec NanoPi R3Saliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000cpus cpu@0cpu,arm,cortex-a55psci%2@DQ^@p} cpu@100cpu,arm,cortex-a55psci%2@DQ^@p} cpu@200cpu,arm,cortex-a55psci%2@DQ^@p} cpu@300cpu,arm,cortex-a55psci%2@DQ^@p} l3-cache,cache'4@Fdisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smcՂ protocol@14hdmi-sound,simple-audio-cardHDMI i2s# =disabledsimple-audio-card,codecDsimple-audio-card,cpuD pmu,arm,cortex-a55-pmu0NY psci ,arm,psci-1.0smcreserved-memory lshmem@10f000,arm,scmi-shmemstimer,arm,armv8-timer0N   zxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob N_ sata-phy =disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob N` sata-phy =disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Nref_clksuspend_clkbus_clkotg utmi_wide=okay usb2-phy8 ?high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Nref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide=okayinterrupt-controller@fd400000 ,arm,gic-v3 @F N MbsA}(l msi-controller@fd440000,arm,gic-v3-itsDYusb@fd800000 ,generic-ehci Nusb =disabledusb@fd840000 ,generic-ohci Nusb =disabledusb@fd880000 ,generic-ehci Nusb =disabledusb@fd8c0000 ,generic-ohci Nusb =disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdWio-domains&,rockchip,rk3568-pmu-io-voltage-domain=okay"syscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru0clock-controller@fdd20000,rockchip,rk3568-cruxin24m0= MG byi2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c N.- i2cpclk default =okayregulator@1c ,tcs,tcs4525vdd_cpu 50!regulator-state-mem(pmic@20,rockchip,rk809 "Ndefault#AY$e$q$}$$$$$$regulatorsDCDC_REG1 vdd_logic pqregulator-state-mem(DCDC_REG2vdd_gpu pqCregulator-state-mem(DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu pqregulator-state-mem(DCDC_REG5vcc_1v8w@w@regulator-state-mem(LDO_REG1vdda0v9_image~~regulator-state-mem(LDO_REG2 vdda_0v9  regulator-state-mem(LDO_REG3 vdda0v9_pmu  regulator-state-mem LDO_REG4 vccio_acodec2Z2Zregulator-state-mem(LDO_REG5 vccio_sdw@2Zregulator-state-mem(LDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem2ZLDO_REG7 vcca_1v8w@w@regulator-state-mem(LDO_REG8 vcca1v8_pmuw@w@regulator-state-memw@LDO_REG9vcca1v8_imagew@w@regulator-state-mem(SWITCH_REG1vcc_3v3regulator-state-mem(SWITCH_REG2 vcc3v3_sd_regulator-state-mem(serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Nt ,baudclkapb_pclk%%&default#0 =disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk'default: =disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(default: =disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)default: =disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk*default: =disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllerE power-domain@7Y+Epower-domain@8 Y,-.Epower-domain@9  Y/01Epower-domain@10 Y234567Epower-domain@11 Y8Epower-domain@13 Y9Epower-domain@14 Y:;<Epower-domain@15Y=>?@AEgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$N()' `jobmmugpugpubus=okayBpCvideo-codec@fdea0400,rockchip,rk3568-vpu N`vdpu aclkhclk|D iommu@fdea0800,rockchip,rk3568-iommu@ N aclkiface Drga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga NZaclkhclksclk&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu N@ aclkhclk|E iommu@fdee0800,rockchip,rk3568-iommu@ N? aclkiface Emmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Nd biuciuciu-driveciu-sampleрreset =disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aN `macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmacethyFGH=okay=bMsY@output rgmii-idIdefaultJKLMNmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22ONdefaultP&N 6 HOIstmmac-axi-configT^nFrx-queues-config~Gqueue0tx-queues-configHqueue0vop@fe040000 0@vopgamma-lut N(%aclkhclkdclk_vp0dclk_vp1dclk_vp2|Q y=okay,rockchip,rk3566-vop=bports port@0 port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? N aclkiface =okayQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi NDpclkdphyR apby =disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi NEpclkdphyS apby =disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  N-((iahbisfrcecrefdefault TUV #y =disabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon +qos@fe138080,rockchip,rk3568-qossyscon :qos@fe138100,rockchip,rk3568-qossyscon ;qos@fe138180,rockchip,rk3568-qossyscon <qos@fe148000,rockchip,rk3568-qossyscon ,qos@fe148080,rockchip,rk3568-qossyscon -qos@fe148100,rockchip,rk3568-qossyscon .qos@fe150000,rockchip,rk3568-qossyscon 8qos@fe158000,rockchip,rk3568-qossyscon 2qos@fe158100,rockchip,rk3568-qossyscon 3qos@fe158180,rockchip,rk3568-qossyscon 4qos@fe158200,rockchip,rk3568-qossyscon 5qos@fe158280,rockchip,rk3568-qossyscon 6qos@fe158300,rockchip,rk3568-qossyscon 7qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon =qos@fe190280,rockchip,rk3568-qossyscon >qos@fe190300,rockchip,rk3568-qossyscon ?qos@fe190380,rockchip,rk3568-qossyscon @qos@fe190400,rockchip,rk3568-qossyscon Aqos@fe198000,rockchip,rk3568-qossyscon 9qos@fe1a8000,rockchip,rk3568-qossyscon /qos@fe1a8080,rockchip,rk3568-qossyscon 0qos@fe1a8100,rockchip,rk3568-qossyscon 1dfi@fe230000,rockchip,rk3568-dfi# N Wpcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<NKJIHG`syspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpcib`XXXX,;YC pcie-phyTl @@pipe =okaydefaultZ HOlegacy-interrupt-controllerbM NHXmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Nb biuciuciu-driveciu-sampleрreset=okayMWizdefault[\]^_mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Nc biuciuciu-driveciu-sampleрreset =disabledspi@fe300000 ,rockchip,sfc0@ Nexvclk_sfchclk_sfc`default =disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 N={}M n6(|zy{}corebusaxiblocktimer=okayM defaultabcdrng@fe388000,rockchip,rk3568-rng8@po coreahbm =disabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ N4==AMFqFq?C9mclk_txmclk_rxhclketxPQ tx-mrx-my =disabled i2s@fe410000,rockchip,rk3568-i2s-tdmA N5=EIMFqFqGK:mclk_txmclk_rxhclkeerxtxRS tx-mrx-mydefault0fghijklmnopq =disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB N6=MMFqOO;mclk_txmclk_rxhclkeetxrxTtx-mydefaultrstu =disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC N7SW<mclk_txmclk_rxhclkeetxrxUV tx-mrx-my =disabledpdm@fe440000,rockchip,rk3568-pdmD NLZYpdm_clkpdm_hclke rxvwxyz{defaultXpdm-m =disabledspdif@fe460000,rockchip,rk3568-spdifF Nf mclkhclk_\etxdefault| =disableddma-controller@fe530000,arm,pl330arm,primecellS@N   apb_pclk%dma-controller@fe550000,arm,pl330arm,primecellU@N  apb_pclkei2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ N/HG i2cpclk}default =okayrtc@51,haoyu,hym8563Qhym8563default~"Ni2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ N0JI i2cpclkdefault  =disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ N1LK i2cpclkdefault  =disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] N2NM i2cpclkdefault  =disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ N3PO i2cpclkdefault  =disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` N tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia NgRQspiclkapb_pclk%%txrxdefault   =disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib NhTSspiclkapb_pclk%%txrxdefault   =disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic NiVUspiclkapb_pclk%%txrxdefault   =disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid NjXWspiclkapb_pclk%%txrxdefault   =disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Nubaudclkapb_pclk%%default#0 =disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Nv# baudclkapb_pclk%%default#0=okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Nw'$baudclkapb_pclk%%default#0 =disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Nx+(baudclkapb_pclk%% default#0 =disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Ny/,baudclkapb_pclk% % default#0 =disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Nz30baudclkapb_pclk% % default#0 =disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk N{74baudclkapb_pclk%%default#0 =disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl N|;8baudclkapb_pclk%%default#0 =disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm N}?<baudclkapb_pclk%%default#0 =disabledthermal-zonescpu-thermal d  'tripscpu_alert0 7p Cpassivecpu_alert1 7$ Cpassivecpu_crit 7s C criticalcooling-mapsmap0 N0 S gpu-thermal   'tripsgpu-threshold 7p Cpassivegpu-target 7$ Cpassivegpu-crit 7s C criticalcooling-mapsmap0 N Stsadc@fe710000,rockchip,rk3568-tsadcq Ns=Mf@ `tsadcapb_pclky bsdefaultsleep y =okaysaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr N]saradcapb_pclk saradc-apb  =disabledpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault: =disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault: =disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault: =disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault: =disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault: =disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault: =disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault: =disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault: =disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault: =disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault: =disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault: =disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault: =disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe="Mphy   =okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe=%Mphy   =okayphy@fe870000,rockchip,rk3568-csi-dphyypclk apby =disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz  apb =disabledRmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{  apb =disabledSusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m N =okayhost-port =okay otg-port =okayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m N  =disabledhost-port  =disabledotg-port  =disabledpinctrl,rockchip,rk3568-pinctrlyW lgpio@fdd60000,rockchip,gpio-bank N!.    Mb"gpio@fe740000,rockchip,gpio-bankt N"cd   Mbgpio@fe750000,rockchip,gpio-banku N#ef  @  Mbgpio@fe760000,rockchip,gpio-bankv N$gh  `  Mbgpio@fe770000,rockchip,gpio-bankw N%ij   MbOpcfg-pull-up !pcfg-pull-down .pcfg-pull-none =pcfg-pull-none-drv-level-1 = Jpcfg-pull-none-drv-level-2 = Jpcfg-pull-none-drv-level-3 = Jpcfg-pull-up-drv-level-1 ! Jpcfg-pull-up-drv-level-2 ! Jpcfg-pull-none-smt = Yacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 ncpuebcedpdpemmcemmc-bus8 n  aemmc-clk nbemmc-cmd ncemmc-datastrobe ndeth0eth1flashfspifspi-pins` n`gmac0gmac1gmac1m0-miim nJgmac1m0-rx-bus20 n   Lgpuhdmitxhdmitxm0-cec nVhdmitx-scl nThdmitx-sda nUi2c0i2c0-xfer n   i2c1i2c1-xfer n  }i2c2i2c2m0-xfer n i2c3i2c3m0-xfer ni2c4i2c4m0-xfer n  i2c5i2c5m0-xfer n  i2s1i2s1m0-lrckrx nii2s1m0-lrcktx nhi2s1m0-sclkrx ngi2s1m0-sclktx nfi2s1m0-sdi0 n ji2s1m0-sdi1 n ki2s1m0-sdi2 n li2s1m0-sdi3 nmi2s1m0-sdo0 nni2s1m0-sdo1 noi2s1m0-sdo2 n pi2s1m0-sdo3 n qi2s2i2s2m0-lrcktx nsi2s2m0-sclktx nri2s2m0-sdi nti2s2m0-sdo nui2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk nvpdmm0-clk1 nwpdmm0-sdi0 n xpdmm0-sdi1 n ypdmm0-sdi2 n zpdmm0-sdi3 n{pmicpmic-int n#pmupwm0pwm0m0-pins n'pwm1pwm1m0-pins n(pwm2pwm2m0-pins n)pwm3pwm3-pins n*pwm4pwm4-pins npwm5pwm5-pins npwm6pwm6-pins npwm7pwm7-pins npwm8pwm8m0-pins n pwm9pwm9m0-pins n pwm10pwm10m0-pins n pwm11pwm11m0-pins npwm12pwm12m0-pins npwm13pwm13m0-pins npwm14pwm14m0-pins npwm15pwm15m0-pins nrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ n[sdmmc0-clk n\sdmmc0-cmd n]sdmmc0-det n^sdmmc1sdmmc2spdifspdifm0-tx n|spi0spi0m0-pins0 n spi0m0-cs0 nspi0m0-cs1 nspi1spi1m0-pins0 n spi1m0-cs0 nspi1m0-cs1 nspi2spi2m0-pins0 nspi2m0-cs0 nspi2m0-cs1 nspi3spi3m0-pins0 n  spi3m0-cs0 nspi3m0-cs1 ntsadctsadc-shutorg ntsadc-pin nuart0uart0-xfer n&uart1uart1m0-xfer n  uart2uart2m0-xfer nuart3uart3m0-xfer nuart4uart4m0-xfer nuart5uart5m0-xfer nuart6uart6m0-xfer nuart7uart7m0-xfer nuart8uart8m0-xfer nuart9uart9m0-xfer nvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac1m0-tx-bus2-level30 n Kgmac1m0-rgmii-bus-level3@ nNgmac-txc-level2gmac1m0-rgmii-clk-level2 nMgpio-ledslan-led-pin npower-led-pin nwan-led-pin ngmaceth-phy-reset-pin nPpciepcie-reset-h nZrockchip-keyreset-button-pin nrtchym8563-int n~usbvcc5v0-usb-host-en nopp-table-0,operating-points-v2 |opp-408000000 Q P P0 @opp-600000000 #F P P0 @opp-816000000 0, P P0 @ opp-1104000000 Aʹ 0 @opp-1416000000 Tfr 0 @opp-1608000000 _" 0 @opp-1800000000 kI 000 @opp-table-1,operating-points-v2Bopp-200000000  P PB@opp-300000000  P PB@opp-400000000 ׄ P PB@opp-600000000 #F B@opp-700000000 )' ~~B@opp-800000000 / B@B@B@chosen serial2:1500000n8gpio-keys ,gpio-keysdefaultbutton-reset reset N"  2gpio-leds ,gpio-ledsdefault led-0  power N" onled-1  lan Nled-2  wan Nregulator-vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z!$regulator-vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@!regulator-vcc5v0_usb,regulator-fixed  "default vcc5v0_usbLK@LK@!regulator-vdd-usbc,regulator-fixed vdd_usbcLK@LK@ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-modephy-handlereset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr50vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cells#io-channel-cellsrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathlabellinux,codedebounce-intervalcolorfunctiondefault-stateenable-active-highgpio