^8X|(PXDrelfor,saibrockchip,rv1109&"7Rockchip RV1109 Relfor Saib Boardaliases=/i2c@ff3f0000B/i2c@ff400000G/i2c@ff520000L/serial@ff560000T/serial@ff410000\/serial@ff570000d/serial@ff580000l/serial@ff590000t/serial@ff5a0000cpuscpu@f00|cpuarm,cortex-a7pscicpu@f01|cpuarm,cortex-a7psciarm-pmuarm,cortex-a7-pmu{|psci arm,psci-1.0smctimerarm,armv7-timer0   n6display_subsystemrockchip,display-subsystemoscillator fixed-clockn6xin24msyscon@fe000000&rockchip,rv1126-grfsysconsimple-mfdsyscon@fe020000)rockchip,rv1126-pmugrfsysconsimple-mfdio-domains&rockchip,rv1126-pmu-io-voltage-domainokay+9GUqos@fe860000rockchip,rv1126-qossyscon qos@fe860080rockchip,rv1126-qossyscon  qos@fe860200rockchip,rv1126-qossyscon  qos@fe86c000rockchip,rv1126-qossyscon  qos@fe8a0000rockchip,rv1126-qossyscon qos@fe8a0080rockchip,rv1126-qossyscon  qos@fe8a0100rockchip,rv1126-qossyscon  qos@fe8a0180rockchip,rv1126-qossyscon interrupt-controller@feff0000 arm,gic-400cx  @ `   power-management@ff3e0000&rockchip,rv1126-pmusysconsimple-mfd>power-controller!rockchip,rv1126-power-controller7power-domain@158ruv  power-domain@16o power-domain@10 PZ[ i2c@ff3f0000(rockchip,rv1126-i2crockchip,rk3399-i2c?  ! i2cpclkdefault disabledi2c@ff400000(rockchip,rv1126-i2crockchip,rk3399-i2c@  " i2cpclkdefault disabledserial@ff410000&rockchip,rv1126-uartsnps,dw-apb-uartA n6  baudclkapb_pclktxrxdefault disabledpwm@ff430000(rockchip,rv1126-pwmrockchip,rk3328-pwmC pwmpclk#defaultokayTpwm@ff430010(rockchip,rv1126-pwmrockchip,rk3328-pwmC pwmpclk#defaultokayUpwm@ff430020(rockchip,rv1126-pwmrockchip,rk3328-pwmC  pwmpclk#defaultokayNpwm@ff430030(rockchip,rv1126-pwmrockchip,rk3328-pwmC0 pwmpclk#default disabledpwm@ff440000(rockchip,rv1126-pwmrockchip,rk3328-pwmD pwmpclk$default disabledpwm@ff440010(rockchip,rv1126-pwmrockchip,rk3328-pwmD pwmpclk$defaultokayPpwm@ff440020(rockchip,rv1126-pwmrockchip,rk3328-pwmD  pwmpclk$defaultokayLpwm@ff440030(rockchip,rv1126-pwmrockchip,rk3328-pwmD0 pwmpclk$default disabledclock-controller@ff480000rockchip,rv1126-pmucruHclock-controller@ff490000rockchip,rv1126-cruIxin24mdma-controller@ff4e0000arm,pl330arm,primecellN@ apb_pclki2c@ff520000(rockchip,rv1126-i2crockchip,rk3399-i2cR " i2cpclkdefault okayrtc@52microcrystal,rv3028R&!"defaultQpwm@ff550000(rockchip,rv1126-pwmrockchip,rk3328-pwmU pwmpclk'#defaultokayOpwm@ff550010(rockchip,rv1126-pwmrockchip,rk3328-pwmU pwmpclk'$defaultokayKpwm@ff550020(rockchip,rv1126-pwmrockchip,rk3328-pwmU  pwmpclk'%defaultokayMpwm@ff550030(rockchip,rv1126-pwmrockchip,rk3328-pwmU0 pwmpclk'&defaultokayJserial@ff560000&rockchip,rv1126-uartsnps,dw-apb-uartV n6baudclkapb_pclktxrxdefault '()okaybluetoothrealtek,rtl8822cs-bt 5* G* T* +,-defaultserial@ff570000&rockchip,rv1126-uartsnps,dw-apb-uartW n6baudclkapb_pclk txrxdefault.okayserial@ff580000&rockchip,rv1126-uartsnps,dw-apb-uartX n6baudclkapb_pclk  txrxdefault/ disabledserial@ff590000&rockchip,rv1126-uartsnps,dw-apb-uartY n6baudclkapb_pclk  txrxdefault0 disabledserial@ff5a0000&rockchip,rv1126-uartsnps,dw-apb-uartZ n6 baudclkapb_pclktxrxdefault1 disabledadc@ff5e0000.rockchip,rv1126-saradcrockchip,rk3399-saradc^ (d, saradcapb_pclkv; }saradc-apbokay2Vtimer@ff660000,rockchip,rv1126-timerrockchip,rk3288-timerf   - pclktimerwatchdog@ff680000 rockchip,rv1126-wdtsnps,dw-wdth  disabledi2s@ff800000rockchip,rv1126-i2s-tdm .=Amclk_txmclk_rxhclktxrxdefault 345vcd }tx-mrx-mokayvop@ffb00000rockchip,rv1126-vop  ;aclk_vopdclk_vophclk_vop }axiahbdclkv67  disabledportendpoint@0endpoint@1iommu@ffb00f00rockchip,iommu ; aclkiface7  disabled6ethernet@ffc40000&rockchip,rv1126-gmacsnps,dwmac-4.20a@_`macirqeth_wake_irq@~Tstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_mac_speedptp_refv }stmmaceth 890: disabledmdiosnps,dwmac-mdiostmmac-axi-configCSc8rx-queues-configm9queue0tx-queues-config:queue0mmc@ffc500000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ N rstbiuciuciu-driveciu-sample 7okay ;<=defaultZmmc@ffc600000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ L lmnbiuciuciu-driveciu-sample  disabledmmc@ffc700000rockchip,rv1126-dw-mshcrockchip,rk3288-dw-mshc@ M opqbiuciuciu-driveciu-sample7okay>$ ?@Adefault*spi@ffc90000 rockchip,sfc@ P8vHĴclk_sfchclk_sfcv7 disabledpinctrlrockchip,rv1126-pinctrl]jgpio@ff460000rockchip,gpio-bankF "&qcxgpio@ff620000rockchip,gpio-bankb #(qcx*gpio@ff630000rockchip,gpio-bankc $)qcx!gpio@ff640000rockchip,gpio-bankd %*qcxHgpio@ff650000rockchip,gpio-banke & +qcxpcfg-pull-upEpcfg-pull-downDpcfg-pull-noneBpcfg-pull-none-drv-level-3Gpcfg-pull-up-drv-level-2Cpcfg-pull-none-drv-level-0-smtFclk_out_ethernetemmcemmc-bus8CCCCCCCC;emmc-clkC=emmc-cmdC<fspii2c0i2c0-xfer  F Fi2c2i2c2-xfer FFi2c3i2c3m2-xfer BB i2s0i2s0m0-lrck-txBi2s0m0-lrck-rxB4i2s0m0-mclkBi2s0m0-sclk-rxB3i2s0m0-sclk-txBi2s0m0-sdi0B5i2s0m0-sdo0Bi2s0m0-sdo1-sdi3Bi2s0m0-sdo2-sdi2Bi2s0m0-sdo3-sdi1Bi2s0m1-lrck-txBi2s0m1-lrck-rx Bi2s0m1-mclkBi2s0m1-sclk-rx Bi2s0m1-sclk-txBi2s0m1-sdi0Bi2s0m1-sdo0Bi2s0m1-sdo1-sdi3 Bi2s0m1-sdo2-sdi2 Bi2s0m1-sdo3-sdi1 Bpwm0pwm1pwm2pwm2m1-pins Bpwm3pwm3m0-pinsBpwm4pwm4m0-pinsBpwm5pwm5m0-pinsBpwm6pwm6m0-pins Bpwm7pwm7m0-pins Bpwm8pwm8m1-pinsB#pwm9pwm9m1-pinsB$pwm10pwm10m1-pinsB%pwm11pwm11m1-pinsB&rgmiisdmmc0sdmmc1sdmmc1-bus4@ C CCCAsdmmc1-clk C?sdmmc1-cmd C@uart0uart0-xfer EE'uart0-ctsnB(uart0-rtsnB)uart1uart1m0-xfer EEuart2uart2m1-xfer EE.uart3uart3m0-xfer EE/uart4uart4m0-xfer EE0uart5uart5m0-xfer EE1bluetooth-pinsbt-resetB+bt-wake-devB,bt-wake-hostD-buttonsswitchEirir-rx BIpwmpwm0m0-pins-pull-upEpwm1m0-pins-pull-upErtcrtc-intE"sdio-pwrseqwifi-enable-hBRgpio-keys gpio-keysbutton A!wGPIO User Switchir-receivergpio-ir-receiver AH defaultIir-transmitter pwm-ir-tx Jled-controllerpwm-leds-multicolormulti-led  indicatorled-0- KPled-1- LPled-2- MPpwm-leds pwm-ledsled-0 NP8noneled-1 OP8noneled-2 PP8nonepwrseq-sdiommc-pwrseq-simpleQ ext_clockdefaultR N*>regulator-vcc-0v8regulator-fixedZvcc_0v8i 5 5Sregulator-vcc-1v2-ddrregulator-fixed Zvcc_1v2_ddriOO$Sregulator-vcc-1v8regulator-fixedZvcc_1v8iw@w@8S2regulator-vcc1v8-irregulator-fixed Zvcc1v8_iriw@w@Sregulator-vcc-2v5-ddrregulator-fixed Zvcc_2v5_ddri&%&%regulator-vcc3v3-sysregulator-fixed Zvcc3v3_sysi2Z2Z$Sregulator-vcc5v0-sysregulator-fixed Zvcc5v0_sysiLK@LK@Sregulator-vdd-armpwm-regulator TZvdd_armi B@FPSregulator-vdd-npu-vepupwm-regulator U Zvdd_npu_vepui ~FPSthermal-sensor1generic-adc-thermalV&sensor-channel7c:Lathermal-sensor2generic-adc-thermalV&sensor-channel7c:La #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c2i2c3serial0serial1serial2serial3serial4serial5device_typeregenable-methodclockscpu-supplyphandleinterruptsinterrupt-affinityclock-frequencyportsclock-output-names#clock-cellsstatuspmuio0-supplypmuio1-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supplyinterrupt-controller#interrupt-cells#power-domain-cellspm_qosrockchip,grfclock-namespinctrl-namespinctrl-0dmasdma-namesreg-shiftreg-io-width#pwm-cells#reset-cells#dma-cellsarm,pl330-periph-burstdevice-wake-gpiosenable-gpioshost-wake-gpios#io-channel-cellsresetsreset-namesvref-supply#sound-dai-cellsrockchip,trcm-sync-rx-onlyiommuspower-domains#iommu-cellsinterrupt-namessnps,mixed-burstsnps,tsosnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,tx-queues-to-usefifo-depthmax-frequencybus-widthnon-removablerockchip,default-sample-phasevmmc-supplycap-sd-highspeedcap-sdio-irqmmc-pwrseqno-mmcno-sdsd-uhs-sdr104assigned-clocksassigned-clock-ratesrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinslinux,codelabellinux,input-typepwmscolorfunctionmax-brightnessactive-lowlinux,default-triggerreset-gpiosregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onstartup-delay-usvin-supplyregulator-settling-time-up-uspwm-supply#thermal-sensor-cellsio-channelsio-channel-namestemperature-lookup-table