8( =firefly,px30-jd4-core-mbfirefly,px30-jd4-corerockchip,px30 +/7Firefly Core-PX30-JD4 on MB-JD4-PX30 baseboardaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/ethernet@ff360000/mmc@ff370000/mmc@ff380000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ!cpu@1cpuarm,cortex-a35psciZ!cpu@2cpuarm,cortex-a35psciZ! cpu@3cpuarm,cortex-a35psciZ! idle-states)pscicpu-sleeparm,idle-state6G^xo!cluster-sleeparm,idle-state6G^o!opp-table-0operating-points-v2!opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem  disabledexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal(>L^ tripstrip-point-0npzpassivetrip-point-1nLzpassive!soc-critn8z criticalcooling-mapsmap0 gpu-thermal(d>^ tripsgpu-thresholdnpzpassivegpu-targetnLzpassive!gpu-critn8z criticalcooling-mapsmap0 xin24m fixed-clockn6xin24m!npower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+!ppower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfd+!io-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&(baudclkapb_pclk4''9txrxCMZdefault h()* disabledi2s@ff060000rockchip,px30-i2s-tdm  (mclk_txmclk_rxhclk4''9txrxr+ tx-mrx-mZdefault0h,-./01234567 disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  (i2s_clki2s_hclk4''9txrxZdefaulth89:; disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s (i2s_clki2s_hclk4''9txrxZdefaulth<=>? disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   !syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+!+io-domains rockchip,px30-io-voltage-domainokay@AB%B@lvdsrockchip,px30-lvdsC"dphyr+,lvds disabledports+port@0+endpoint@0<D!endpoint@1<E!port@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I(baudclkapb_pclk4''9txrxCMZdefault hFGH disabledserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J(baudclkapb_pclk4''9txrxCMZdefaulthIokayserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K(baudclkapb_pclk4''9txrxCMZdefault hJKL disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L(baudclkapb_pclk4'' 9txrxCMZdefault hMNO disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M(baudclkapb_pclk4' ' 9txrxCMZdefault hPQR disabledi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN (i2cpclk ZdefaulthS+okaypmic@20rockchip,rk809  TZdefaulthULdxin32krV~VVVWWWWVregulatorsDCDC_REG1vdd_log~pq2F!regulator-state-memXp~DCDC_REG2vdd_arm~pq2F!regulator-state-memp~DCDC_REG3vcc_ddr2Fregulator-state-memXDCDC_REG4vcc_3v0--2F!Bregulator-state-memXp-DCDC_REG5 vcc3v3_sys2Z2Z2F!Wregulator-state-memXp2ZLDO_REG1vcc_1v0B@B@2Fregulator-state-memXpB@LDO_REG2vcc_1v8w@w@2F!@regulator-state-memXpw@LDO_REG3vdd_1v0B@B@2Fregulator-state-memXpB@LDO_REG4 vcc3v0_pmu--2F!%regulator-state-memXp-LDO_REG5 vccio_sdw@2Z2F!Aregulator-state-memXp2ZLDO_REG6vcc_sd2Z2ZF!zregulator-state-memXp2ZLDO_REG7 vcc2v8_dvp**Fregulator-state-memp*LDO_REG8 vcc1v8_dvpw@w@Fregulator-state-memXpw@LDO_REG9 vcc1v5_dvp``Fregulator-state-memp`SWITCH_REG1 vcc3v3_lcdFSWITCH_REG2 vcc5v0_host2Fi2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO (i2cpclk ZdefaulthX+ disabledi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP (i2cpclk  ZdefaulthY+ disabledi2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q (i2cpclk  ZdefaulthZ+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U(spiclkapb_pclk4' ' 9txrxZdefaulth[\]^+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V(spiclkapb_pclk4''9txrxZdefaulth_`abc+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ % disabledpwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthd disabledpwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthe disabledpwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S (pwmpclkZdefaulthf disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S (pwmpclkZdefaulthg disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthh disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthi disabledpwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T (pwmpclkZdefaulthj disabledpwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T (pwmpclkZdefaulthk disabledtimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& (pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ (apb_pclk!'tsadc@ff280000rockchip,px30-tsadc( $,P,X(tsadcapb_pclk tsadc-apbr+Zinitdefaultsleephlml)okay?V! saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( Tq-W(saradcapb_pclk saradc-apbokay@!nvmem@ff290000rockchip,px30-otp)@/Za(otpapb_pclkphyphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ n& (xin24mgpllr+8@IFq рр !clock-controller@ff2bc000rockchip,px30-pmucru+n(xin24mr+&&& G!&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & (phyclko usb480m_phyokay!ohost-port D linestateokay!rotg-port$BA@otg-bvalidotg-idlinestateokay!qphy@ff2e0000rockchip,px30-dsi-dphy.& E (refpclk>apbp  disabled!Cphy@ff2f0000rockchip,px30-csi-dphy/@F(pclkp /apbr+ disabled!usb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >(otgotg @ q "usb2-phypokayusb@ff340000 generic-ehci4 <r"usbpokayusb@ff350000 generic-ohci5 =r"usbpokayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[(stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedr+rmiiZdefaulthstp ^ stmmacethokay"output/B :u J `PPmdiosnps,dwmac-mdio+mmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD(biuciuciu-driveciu-sampleuрZdefaulthvwxypokay zAmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF(biuciuciu-driveciu-sampleuрZdefault h{|}p okay1?~mmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH(biuciuciu-driveciu-sampleuрZdefault hp okayJ1?B@spi@ff3a0000 rockchip,sfc:@ 8:(clk_sfchclk_sfc hZdefaultp  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97(ahbnfc7рZdefault hp  disabledopp-table-1operating-points-v2!opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIpokayY!video-codec@ff442000rockchip,px30-vpuD PO vepuvdpu (aclkhclkep iommu@ff442800rockchip,iommuD( Q (aclkifacelp !dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD(pclkC"dphyp =apbr++ disabledports+port@0+endpoint@0<!endpoint@1<!port@1vop@ff460000rockchip,px30-vop-bigF M(aclk_vopdclk_vophclk_vop345 axiahbdclkep  disabledport+! endpoint@0<!endpoint@1<!Diommu@ff460f00rockchip,iommuF M (aclkifacep l disabled!vop@ff470000rockchip,px30-vop-litG N(aclk_vopdclk_vophclk_vop789 axiahbdclkep  disabledport+! endpoint@0<!endpoint@1<!Eiommu@ff470f00rockchip,iommuG N (aclkifacep l disabled!isp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_(ispaclkhclkpclke"dphyp  disabledports+port@0iommu@ff4a8000rockchip,iommuJ F (aclkifacep yl!qos@ff518000rockchip,px30-qossysconQ !qos@ff520000rockchip,px30-qossysconR !$qos@ff52c000rockchip,px30-qossysconR !qos@ff538000rockchip,px30-qossysconS !qos@ff538080rockchip,px30-qossysconS !qos@ff538100rockchip,px30-qossysconS !qos@ff538180rockchip,px30-qossysconS !qos@ff540000rockchip,px30-qossysconT !qos@ff540080rockchip,px30-qossysconT !qos@ff548000rockchip,px30-qossysconT !qos@ff548080rockchip,px30-qossysconT ! qos@ff548100rockchip,px30-qossysconT !!qos@ff548180rockchip,px30-qossysconT !"qos@ff548200rockchip,px30-qossysconT !#qos@ff550000rockchip,px30-qossysconU !qos@ff550080rockchip,px30-qossysconU !qos@ff550100rockchip,px30-qossysconU !qos@ff550180rockchip,px30-qossysconU !qos@ff558000rockchip,px30-qossysconU !qos@ff558080rockchip,px30-qossysconU !pinctrlrockchip,px30-pinctrlr++gpio@ff040000rockchip,gpio-bank &!Tgpio@ff250000rockchip,gpio-bank% \!gpio@ff260000rockchip,gpio-bank& ]!ugpio@ff270000rockchip,gpio-bank' ^pcfg-pull-up!pcfg-pull-downpcfg-pull-none!pcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4ma!pcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8ma!pcfg-pull-up-8ma!pcfg-pull-none-12ma !pcfg-pull-up-12ma !pcfg-pull-none-smt!pcfg-output-high pcfg-output-low pcfg-input-high (!pcfg-input (i2c0i2c0-xfer 5 !Si2c1i2c1-xfer 5!Xi2c2i2c2-xfer 5!Yi2c3i2c3-xfer 5  !Ztsadctsadc-otp-pin 5!ltsadc-otp-out 5!muart0uart0-xfer 5  !(uart0-cts 5 !)uart0-rts 5 !*uart1uart1-xfer 5!Fuart1-cts 5!Guart1-rts 5!Huart2-m0uart2m0-xfer 5uart2-m1uart2m1-xfer 5 !Iuart3-m0uart3m0-xfer 5uart3m0-cts 5uart3m0-rts 5uart3-m1uart3m1-xfer 5!Juart3m1-cts 5 !Kuart3m1-rts 5 !Luart4uart4-xfer 5!Muart4-cts 5!Nuart4-rts 5!Ouart5uart5-xfer 5!Puart5-cts 5!Quart5-rts 5!Rspi0spi0-clk 5![spi0-csn 5!\spi0-miso 5 !]spi0-mosi 5 !^spi0-clk-hs 5spi0-miso-hs 5 spi0-mosi-hs 5 spi1spi1-clk 5!_spi1-csn0 5 !`spi1-csn1 5 !aspi1-miso 5!bspi1-mosi 5 !cspi1-clk-hs 5spi1-miso-hs 5spi1-mosi-hs 5 pdmpdm-clk0m0 5pdm-clk0m1 5pdm-clk1 5pdm-sdi0m0 5pdm-sdi0m1 5pdm-sdi1 5pdm-sdi2 5pdm-sdi3 5pdm-clk0m0-sleep 5pdm-clk0m1-sleep 5pdm-clk1-sleep 5pdm-sdi0m0-sleep 5pdm-sdi0m1-sleep 5pdm-sdi1-sleep 5pdm-sdi2-sleep 5pdm-sdi3-sleep 5i2s0i2s0-8ch-mclk 5i2s0-8ch-sclktx 5!,i2s0-8ch-sclkrx 5 !-i2s0-8ch-lrcktx 5!.i2s0-8ch-lrckrx 5 !/i2s0-8ch-sdo0 5!0i2s0-8ch-sdo1 5!2i2s0-8ch-sdo2 5!4i2s0-8ch-sdo3 5!6i2s0-8ch-sdi0 5!1i2s0-8ch-sdi1 5 !3i2s0-8ch-sdi2 5 !5i2s0-8ch-sdi3 5!7i2s1i2s1-2ch-mclk 5i2s1-2ch-sclk 5!8i2s1-2ch-lrck 5!9i2s1-2ch-sdi 5!:i2s1-2ch-sdo 5!;i2s2i2s2-2ch-mclk 5i2s2-2ch-sclk 5!<i2s2-2ch-lrck 5!=i2s2-2ch-sdi 5!>i2s2-2ch-sdo 5!?sdmmcsdmmc-clk 5!vsdmmc-cmd 5!wsdmmc-det 5!xsdmmc-bus1 5sdmmc-bus4@ 5!ysdiosdio-clk 5!}sdio-cmd 5!|sdio-bus4@ 5!{emmcemmc-clk 5 !emmc-cmd 5 !emmc-rstnout 5 emmc-bus1 5emmc-bus4@ 5emmc-bus8 5!emmc-reset 5 !flashflash-cs0 5!flash-rdy 5 !flash-dqs 5 !flash-ale 5 !flash-cle 5 !flash-wrn 5 !flash-csl 5flash-rdn 5!flash-bus8 5!sfcsfc-bus4@ 5!sfc-bus2 5sfc-cs0 5!sfc-clk 5 !lcdclcdc-rgb-dclk-pin 5lcdc-rgb-m0-hsync-pin 5lcdc-rgb-m0-vsync-pin 5lcdc-rgb-m0-den-pin 5lcdc-rgb888-m0-data-pins 5     lcdc-rgb666-m0-data-pins 5     lcdc-rgb565-m0-data-pins 5     lcdc-rgb888-m1-data-pins 5   lcdc-rgb666-m1-data-pins 5   lcdc-rgb565-m1-data-pins 5   pwm0pwm0-pin 5!dpwm1pwm1-pin 5!epwm2pwm2-pin 5 !fpwm3pwm3-pin 5!gpwm4pwm4-pin 5!hpwm5pwm5-pin 5!ipwm6pwm6-pin 5!jpwm7pwm7-pin 5!kgmacrmii-pins 5 !smac-refclk-12ma 5 !tmac-refclk 5 cif-m0cif-clkout-m0 5 dvp-d2d9-m0 5   dvp-d0d1-m0 5 d10-d11-m0 5cif-m1cif-clkout-m1 5dvp-d2d9-m1 5  dvp-d0d1-m1 5d10-d11-m1 5ispisp-prelight 5pmicpmic_int 5!Uledsblue-led 5 !green-led 5 !sdio-pwrseqwifi-enable-h 5!emmc-pwrseqmmc-pwrseq-emmchZdefault C !regulator-vcc5v0-sysregulator-fixed vcc5v0_sys2FLK@LK@ O!Vchosen Zserial2:115200n8regulator-dc-12vregulator-fixeddc_12v2F!adc-keys adc-keys f rbuttons ` dbutton-recovery Recovery h FPleds gpio-ledsZdefaulthblue-led  on heartbeat I  px30-mb-jd4:blue:work heartbeatgreen-led  on power I  px30-mb-jd4:blue:diy default-onsdio-pwrseqmmc-pwrseq-simpleZdefaulth CT!~regulator-vcc5v0-baseboardregulator-fixedvcc5v0_baseboard2FLK@LK@ O! compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1ethernet0mmc0mmc1mmc2device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendnum-cs#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplykeep-power-in-suspendnon-removablemmc-pwrseqmmc-hs200-1_8vmali-supplyiommus#iommu-cellsrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsreset-gpiosvin-supplystdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltcolordefault-statefunctionlinux,default-trigger