8H( }$rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff550000/mmc@ff500000/mmc@ff510000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci @+8E@Wdu cpu@1cpuarm,cortex-a53xpsci @+8E@Wdu cpu@2cpuarm,cortex-a53xpsci @+8E@Wdu cpu@3cpuarm,cortex-a53xpsci @+8E@Wdu idle-statespscicpu-sleeparm,idle-statexl2-cachecache@-opp-table-0operating-points-v2 opp-408000000Q~)@:opp-600000000#F~)@opp-8160000000,B@)@opp-1008000000<)@opp-1200000000G()@opp-1296000000M?d )@analog-soundsimple-audio-cardFi2s_yAnalog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem hdmi-soundsimple-audio-cardFi2s_yHDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mBi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk  txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclktxrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclktxrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk tx!default/ disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrx!defaultsleep/9 disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd7io-domains"rockchip,rk3328-io-voltage-domain disabledgpiorockchip,rk3328-grf-gpioCSpower-controller!rockchip,rk3328-power-controller_+9power-domain@6D_power-domain@5 BAB_power-domain@8F_reboot-modesyscon-reboot-modeszRBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclktxrx!default / disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclktxrx!default / ! disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclktxrx!default/"okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk!default/# disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk!default/$okaypmic@18rockchip,rk805 %xin32krk805-clkout2CS!default/&''''()(regulatorsDCDC_REG1 5vdd_logicD 4\ tregulator-state-memB@DCDC_REG25vdd_armD 4\ tregulator-state-mem~DCDC_REG35vcc_ddrtregulator-state-memDCDC_REG45vcc_ioD2Z\2Zt(regulator-state-mem2ZLDO_REG15vcc_18Dw@\w@tregulator-state-memw@LDO_REG2 5vcc18_emmcDw@\w@tregulator-state-memw@LDO_REG35vdd_10DB@\B@tregulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk!default/) disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk!default/* disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk txrx!default/+,-. disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk!default// disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk!default/0 disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk!default/1 disabledpwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk!default/2 disableddma-controller@ff1f0000arm,pl330arm,primecell@ apb_pclkthermal-zonessoc-thermal13tripstrip-point0ApMpassivetrip-point1ALMpassive4soc-critAsM criticalcooling-mapsmap0X40] ltsadc@ff250000rockchip,rk3328-tsadc% :y$P$tsadcapb_pclk!initdefaultsleep/5965B tsadc-apb7okay3efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1a Cadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclkV saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\" gpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 ` aclkiface0 disablediommu@ff340800rockchip,iommu4@ bF aclkiface0 disabledvideo-codec@ff350000rockchip,rk3328-vpu5   vdpuF aclkhclk=8D9iommu@ff350800rockchip,iommu5@  F aclkiface0D98video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreyAB ׄׄ=:D9iommu@ff360480rockchip,iommu 6@6@ JB aclkiface0D9:vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop axiahbdclk=; disabledport+ endpoint@0R<Aiommu@ff373f00rockchip,iommu7?  ; aclkiface0 disabled;hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #Fiahbisfrcecb=ghdmi!default />?@7 disabledports+port@0endpointRA<port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk7 disabledphy@ff430000rockchip,rk3328-hdmi-phyC SBysysclkrefoclkrefpclk hdmi_phyqC }cpu-version disabled=clock-controller@ff440000rockchip,rk3328-cruDBxin24m7yx=&'(ABDC"\5H4$zBBB|n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyBphyclk usb480m_phyy{DokayDotg-port$;<= otg-bvalidotg-idlinestateokayUhost-port >  linestateokayVmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-sampleрmresetokay!default/EFGHImmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-sampleрnresetokay'=JH!default /KLMmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-sampleрoresetokayH!default /NOPethernet@ff540000rockchip,rk3328-gmacT  macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth7Vdr disabledethernet@ff550000rockchip,rk3328-gmacU7  macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmaceth}rmiiQVdroutputokayRyeTmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22Vd!default/STQusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motgotg@ bU gusb2-phyokayusb@ff5c0000 generic-ehci\  NDbVgusbokayusb@ff5d0000 generic-ohci]  NDbVgusbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-sampleрhreset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkotg utmi_wide1Ik disabledinterrupt-controller@ff811000 arm,gic-400@ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl7+gpio@ff210000rockchip,gpio-bank! 3CSdgpio@ff220000rockchip,gpio-bank" 4CScgpio@ff230000rockchip,gpio-bank# 5CS%gpio@ff240000rockchip,gpio-bank$ 6CSpcfg-pull-upYpcfg-pull-downapcfg-pull-none Wpcfg-pull-none-2ma  `pcfg-pull-up-2ma pcfg-pull-up-4ma Zpcfg-pull-none-4ma  ]pcfg-pull-down-4ma pcfg-pull-none-8ma  [pcfg-pull-up-8ma \pcfg-pull-none-12ma   ^pcfg-pull-up-12ma  _pcfg-output-high #pcfg-output-low /pcfg-input-high :Xpcfg-input :i2c0i2c0-xfer GWW#i2c1i2c1-xfer GWW$i2c2i2c2-xfer G WW)i2c3i2c3-xfer GWW*i2c3-pins GWWhdmi_i2chdmii2c-xfer GWW?pdm-0pdmm0-clk GWpdmm0-fsync GWpdmm0-sdi0 GWpdmm0-sdi1 GWpdmm0-sdi2 GWpdmm0-sdi3 GWpdmm0-clk-sleep GXpdmm0-sdi0-sleep GXpdmm0-sdi1-sleep GXpdmm0-sdi2-sleep GXpdmm0-sdi3-sleep GXpdmm0-fsync-sleep GXtsadcotp-pin G W5otp-out G W6uart0uart0-xfer G WYuart0-cts G Wuart0-rts G Wuart0-rts-pin G Wuart1uart1-xfer GWYuart1-cts GW uart1-rts GW!uart1-rts-pin GWuart2-0uart2m0-xfer GWYuart2-1uart2m1-xfer GWY"spi0-0spi0m0-clk GYspi0m0-cs0 G Yspi0m0-tx G Yspi0m0-rx G Yspi0m0-cs1 G Yspi0-1spi0m1-clk GYspi0m1-cs0 GYspi0m1-tx GYspi0m1-rx GYspi0m1-cs1 GYspi0-2spi0m2-clk GY+spi0m2-cs0 GY.spi0m2-tx GY,spi0m2-rx GY-i2s1i2s1-mclk GWi2s1-sclk GWi2s1-lrckrx GWi2s1-lrcktx GWi2s1-sdi GWi2s1-sdo GWi2s1-sdio1 GWi2s1-sdio2 GWi2s1-sdio3 GWi2s1-sleep GXXXXXXXXXi2s2-0i2s2m0-mclk GWi2s2m0-sclk GWi2s2m0-lrckrx GWi2s2m0-lrcktx GWi2s2m0-sdi GWi2s2m0-sdo GWi2s2m0-sleep` GXXXXXXi2s2-1i2s2m1-mclk GWi2s2m1-sclk GWi2sm1-lrckrx GWi2s2m1-lrcktx GWi2s2m1-sdi GWi2s2m1-sdo GWi2s2m1-sleepP GXXXXXspdif-0spdifm0-tx GWspdif-1spdifm1-tx GWspdif-2spdifm2-tx GWsdmmc0-0sdmmc0m0-pwren GZsdmmc0m0-pin GZsdmmc0-1sdmmc0m1-pwren GZsdmmc0m1-pin GZesdmmc0sdmmc0-clk G[Esdmmc0-cmd G\Fsdmmc0-dectn GZGsdmmc0-wrprt GZsdmmc0-bus1 G\sdmmc0-bus4@ G\\\\Hsdmmc0-pins GZZZZZZZZsdmmc0extsdmmc0ext-clk G]sdmmc0ext-cmd GZsdmmc0ext-wrprt GZsdmmc0ext-dectn GZsdmmc0ext-bus1 GZsdmmc0ext-bus4@ GZZZZsdmmc0ext-pins GZZZZZZZZsdmmc1sdmmc1-clk G [Msdmmc1-cmd G \Lsdmmc1-pwren G\sdmmc1-wrprt G\sdmmc1-dectn G\sdmmc1-bus1 G\sdmmc1-bus4@ G\\\\Ksdmmc1-pins G Z ZZZZZZZZemmcemmc-clk G^Nemmc-cmd G_Oemmc-pwren GWemmc-rstnout GWemmc-bus1 G_emmc-bus4@ G____emmc-bus8 G________Ppwm0pwm0-pin GW/pwm1pwm1-pin GW0pwm2pwm2-pin GW1pwmirpwmir-pin GW2gmac-1rgmiim1-pins` G [ ]][]]] ] ][ []][[[ [][[[[rmiim1-pins G`^```` ` `^ ^ W WWWWWgmac2phyfephyled-speed10 GWfephyled-duplex GWfephyled-rxm1 GWSfephyled-txm1 GWfephyled-linkm1 GWTtsadc_pintsadc-int G Wtsadc-pin G Whdmi_pinhdmi-cec GW>hdmi-hpd Ga@cif-0dvp-d2d9-m0 GWWWWW W W WWWWWcif-1dvp-d2d9-m1 GWWWWWWWWWWWWpmicpmic-int-l GY&sdio-pwrseqwifi-enable-h GWbchosen Userial2:1500000n8regulator-dc-12vregulator-fixed5dc_12vtD\fsdio-pwrseqmmc-pwrseq-simple!default/b acJregulator-sdmmcregulator-fixed md!default/e5vcc_sdD2Z\2Z r(Iregulator-vcc-sysregulator-fixed5vcc_systDLK@\LK@ rf'regulator-vcc-phyregulator-fixed5vcc_phytR compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply