,8@( ,friendlyarm,nanopi-r2s-plusrockchip,rk3328 +7FriendlyElec NanoPi R2S Plusaliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/usb@ff600000/device@2/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci@0=J@\iz cpu@1cpuarm,cortex-a53xpsci@0=J@\iz cpu@2cpuarm,cortex-a53xpsci@0=J@\iz cpu@3cpuarm,cortex-a53xpsci@0=J@\iz idle-statespscicpu-sleeparm,idle-statexl2-cachecache @2opp-table-0operating-points-v2opp-408000000Q ~.@?opp-600000000#F ~.@opp-8160000000, B@.@opp-1008000000< .@opp-1200000000G (.@opp-1296000000M?d  .@analog-soundsimple-audio-cardKi2sd~Analog disabledsimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg display-subsystemrockchip,display-subsystem  disabledhdmi-soundsimple-audio-cardKi2sd~HDMI disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7i2s_clki2s_hclk   txrx disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8i2s_clki2s_hclk txrx disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9i2s_clki2s_hclk txrx disabledspdif@ff030000rockchip,rk3328-spdif .: mclkhclk  tx&default4 disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclk rx&defaultsleep4> disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd:io-domains"rockchip,rk3328-io-voltage-domainokayHUcqgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+<power-domain@6Dpower-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-modeRBRBRB  RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&baudclkapb_pclk txrx&default 4 !"# disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'baudclkapb_pclk txrx&default 4#$%# disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(baudclkapb_pclk txrx&default4&#okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 i2cpclk&default4' disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 i2cpclk&default4(okaypmic@18rockchip,rk805 )xin32krk805-clkout24*&default-ES+_+k+w++regulatorsDCDC_REG1vdd_log 4 0regulator-state-mem-B@DCDC_REG2vdd_arm 4 0regulator-state-mem-~DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4 vcc_io_332Z2Zregulator-state-mem-2ZLDO_REG1vcc_18w@w@regulator-state-mem-w@LDO_REG2 vcc18_emmcw@w@regulator-state-mem-w@LDO_REG3vdd_10B@B@regulator-state-mem-B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 i2cpclk&default4, disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: i2cpclk&default4- disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ spiclkapb_pclk  txrx&default4./01 disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< pwmpclk&default42I disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclk&default43I disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclk&default44Iokaypwm@ff1b0030rockchip,rk3328-pwm0< pwmpclk&default45I disableddma-controller@ff1f0000arm,pl330arm,primecell@T apb_pclkkthermal-zonessoc-thermalv6tripstrip-point0ppassivetrip-point1Lpassive7soc-crits criticalcooling-mapsmap070 tsadc@ff250000rockchip,rk3328-tsadc% :$P$tsadcapb_pclk&initdefaultsleep48>98#B *tsadc-apb6:CZokayp6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%saradcapb_pclk#V *saradc-apb disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscore#fiommu@ff330200rockchip,iommu3 ` aclkiface disablediommu@ff340800rockchip,iommu4@ bF aclkiface disabledvideo-codec@ff350000rockchip,rk3328-vpu5  vdpuF aclkhclk;<iommu@ff350800rockchip,iommu5@  F aclkiface<;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABaxiahbcabaccoreAB ׄׄ=<iommu@ff360480rockchip,iommu 6@6@ JB aclkiface<=vop@ff370000rockchip,rk3328-vop7>  x;aclk_vopdclk_vophclk_vop# *axiahbdclk> disabledport+ endpoint@0?Diommu@ff373f00rockchip,iommu7?  ; aclkiface disabled>hdmi@ff3c0000rockchip,rk3328-dw-hdmi< #Fiahbisfrcec@hdmi&default 4ABC6: disabledports+port@0endpointD?port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk6: disabledphy@ff430000rockchip,rk3328-hdmi-phyC SEysysclkrefoclkrefpclk hdmi_phyF *cpu-version; disabled@clock-controller@ff440000rockchip,rk3328-cruDExin24m6:Fx=&'(ABDC"\5H4$SzEEE|n6n6n6ׄn6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk usb480m_phy{SGokayGotg-port;$;<=otg-bvalidotg-idlinestateokayWhost-port; > linestateokayXmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNbiuciuciu-driveciu-samplejuр#m*resetokay4HIJK&defaultLmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KObiuciuciu-driveciu-samplejuр#n*reset disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPbiuciuciu-driveciu-samplejuр#o*resetokay &default 4MNOethernet@ff540000rockchip,rk3328-gmacT macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac#c *stmmaceth6:&4BokaydfSPPMinputZrgmiic4Q&defaultnRy$mdiosnps,dwmac-mdio+ethernet-phy@14S&default'P )Rethernet@ff550000rockchip,rk3328-gmacU6: macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy#b *stmmacethZrmiinT&4BMoutput disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22V#d&default4UVTusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Motghost@ W usb2-phyokayusb@ff5c0000 generic-ehci\  NGXusbokayusb@ff5d0000 generic-ohci]  NGXusbokaymmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc_@  @MQbiuciuciu-driveciu-samplejuр#h*reset disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`aref_clksuspend_clkbus_clkhost utmi_wide  - E g  okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `   crypto@ff060000rockchip,rk3328-crypto@ PQ;hclk_masterhclk_slavesclk#D *crypto-rstpinctrlrockchip,rk3328-pinctrl6:+ gpio@ff210000rockchip,gpio-bank! 3  egpio@ff220000rockchip,gpio-bank" 4  )gpio@ff230000rockchip,gpio-bank# 5  igpio@ff240000rockchip,gpio-bank$ 6  pcfg-pull-up [pcfg-pull-down cpcfg-pull-none Ypcfg-pull-none-2ma  bpcfg-pull-up-2ma  pcfg-pull-up-4ma  \pcfg-pull-none-4ma  _pcfg-pull-down-4ma  pcfg-pull-none-8ma  ]pcfg-pull-up-8ma  ^pcfg-pull-none-12ma   `pcfg-pull-up-12ma   apcfg-output-high pcfg-output-low +pcfg-input-high  6Zpcfg-input 6i2c0i2c0-xfer CYY'i2c1i2c1-xfer CYY(i2c2i2c2-xfer C YY,i2c3i2c3-xfer CYY-i2c3-pins CYYhdmi_i2chdmii2c-xfer CYYBpdm-0pdmm0-clk CYpdmm0-fsync CYpdmm0-sdi0 CYpdmm0-sdi1 CYpdmm0-sdi2 CYpdmm0-sdi3 CYpdmm0-clk-sleep CZpdmm0-sdi0-sleep CZpdmm0-sdi1-sleep CZpdmm0-sdi2-sleep CZpdmm0-sdi3-sleep CZpdmm0-fsync-sleep CZtsadcotp-pin C Y8otp-out C Y9uart0uart0-xfer C Y[ uart0-cts C Y!uart0-rts C Y"uart0-rts-pin C Yuart1uart1-xfer CY[#uart1-cts CY$uart1-rts CY%uart1-rts-pin CYuart2-0uart2m0-xfer CY[uart2-1uart2m1-xfer CY[&spi0-0spi0m0-clk C[spi0m0-cs0 C [spi0m0-tx C [spi0m0-rx C [spi0m0-cs1 C [spi0-1spi0m1-clk C[spi0m1-cs0 C[spi0m1-tx C[spi0m1-rx C[spi0m1-cs1 C[spi0-2spi0m2-clk C[.spi0m2-cs0 C[1spi0m2-tx C[/spi0m2-rx C[0i2s1i2s1-mclk CYi2s1-sclk CYi2s1-lrckrx CYi2s1-lrcktx CYi2s1-sdi CYi2s1-sdo CYi2s1-sdio1 CYi2s1-sdio2 CYi2s1-sdio3 CYi2s1-sleep CZZZZZZZZZi2s2-0i2s2m0-mclk CYi2s2m0-sclk CYi2s2m0-lrckrx CYi2s2m0-lrcktx CYi2s2m0-sdi CYi2s2m0-sdo CYi2s2m0-sleep` CZZZZZZi2s2-1i2s2m1-mclk CYi2s2m1-sclk CYi2sm1-lrckrx CYi2s2m1-lrcktx CYi2s2m1-sdi CYi2s2m1-sdo CYi2s2m1-sleepP CZZZZZspdif-0spdifm0-tx CYspdif-1spdifm1-tx CYspdif-2spdifm2-tx CYsdmmc0-0sdmmc0m0-pwren C\sdmmc0m0-pin C\sdmmc0-1sdmmc0m1-pwren C\sdmmc0m1-pin C\ksdmmc0sdmmc0-clk C]Hsdmmc0-cmd C^Isdmmc0-dectn C\Jsdmmc0-wrprt C\sdmmc0-bus1 C^sdmmc0-bus4@ C^^^^Ksdmmc0-pins C\\\\\\\\sdmmc0extsdmmc0ext-clk C_sdmmc0ext-cmd C\sdmmc0ext-wrprt C\sdmmc0ext-dectn C\sdmmc0ext-bus1 C\sdmmc0ext-bus4@ C\\\\sdmmc0ext-pins C\\\\\\\\sdmmc1sdmmc1-clk C ]sdmmc1-cmd C ^sdmmc1-pwren C^sdmmc1-wrprt C^sdmmc1-dectn C^sdmmc1-bus1 C^sdmmc1-bus4@ C^^^^sdmmc1-pins C \ \\\\\\\\emmcemmc-clk C`Memmc-cmd CaNemmc-pwren CYemmc-rstnout CYemmc-bus1 Caemmc-bus4@ Caaaaemmc-bus8 CaaaaaaaaOpwm0pwm0-pin CY2pwm1pwm1-pin CY3pwm2pwm2-pin CY4pwmirpwmir-pin CY5gmac-1rgmiim1-pins` C ] __]___ _ _] ]__]]] ]_]]]]Qrmiim1-pins Cb`bbbb b b` ` Y YYYYYgmac2phyfephyled-speed10 CYfephyled-duplex CYfephyled-rxm1 CYUfephyled-txm1 CYfephyled-linkm1 CYVtsadc_pintsadc-int C Ytsadc-pin C Yhdmi_pinhdmi-cec CYAhdmi-hpd CcCcif-0dvp-d2d9-m0 CYYYYY Y Y YYYYYcif-1dvp-d2d9-m1 CYYYYYYYYYYYYbuttonreset-button-pin CYdgmac2ioeth-phy-reset-pin CcSledslan-led-pin CYfsys-led-pin CYgwan-led-pin CYhlanlan-vdd-pin CYlpmicpmic-int-l C[*sdsdio-vcc-pin C[jchosen Qserial2:1500000n8gmac-clock fixed-clocksY@ gmac_clkinPkeys gpio-keys4d&defaultkey-reset ]reset e c n2leds gpio-leds 4fgh&defaultled-0 i ]nanopi-r2s:green:lanled-1 e ]nanopi-r2s:red:sys onled-2 i ]nanopi-r2s:green:wanregulator-sdmmcioregulator-gpio  )4j&default vcc_io_sdiow@2Z  voltage w@2Z regulator-sdmmcregulator-fixed e4k&defaultvcc_sd2Z2Z Lregulator-vdd-5vregulator-fixedvdd_5vLK@LK@+regulator-vdd-5v-lanregulator-fixed  i4l&default vdd_5v_lan + compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vnon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-modephy-supplyphy-handletx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio