8L( ,anbernic,rg503rockchip,rk35667handsetDAnbernic RG503aliasesJ/pinctrl/gpio@fdd60000P/pinctrl/gpio@fe740000V/pinctrl/gpio@fe750000\/pinctrl/gpio@fe760000b/pinctrl/gpio@fe770000h/i2c@fdd40000m/i2c@fe5a0000r/i2c@fe5b0000w/i2c@fe5c0000|/i2c@fe5d0000/i2c@fe5e0000/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe2b0000/mmc@fe2c0000/mmc@fe000000cpus cpu@0cpu,arm,cortex-a55 psci-:@LYf@x cpu@100cpu,arm,cortex-a55psci-:@LYf@x cpu@200cpu,arm,cortex-a55psci-:@LYf@x cpu@300cpu,arm,cortex-a55psci-:@LYf@x l3-cache,cache/<@Ndisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc݂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s+Eokaysimple-audio-card,codecLsimple-audio-card,cpuL pmu,arm,cortex-a55-pmu0Va psci ,arm,psci-1.0&smcreserved-memory tshmem@10f000,arm,scmi-shmem{timer,arm,armv8-timer0V   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@ satapmaliverxoob V_ sata-phy Edisabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci satapmaliverxoob V` sata-phy Edisabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ V ref_clksuspend_clkbus_clk peripheral utmi_wide 'Eokay usb2-phy@ Ghigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ V ref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide 'Eokayinterrupt-controller@fd400000 ,arm,gic-v3 @F V Uj{A(t msi-controller@fd440000,arm,gic-v3-itsD^usb@fd800000 ,generic-ehci V usb Edisabledusb@fd840000 ,generic-ohci V usb Edisabledusb@fd880000 ,generic-ehci V usbEokayusb@fd8c0000 ,generic-ohci V usbEokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd\io-domains&,rockchip,rk3568-pmu-io-voltage-domainEokaysyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfdsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru*clock-controller@fdd20000,rockchip,rk3568-cru xin24m* 7GG e\si2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c V. - i2cpclk default Eokaypmic@20,rockchip,rk817 !Vrk808-clkout1rk808-clkout2mclk H7H\default"#$$$$$$$$%regulatorsDCDC_REG1 1 Ipaqv vdd_logicregulator-state-mem DCDC_REG2 1 Ipaqvvdd_gpuEregulator-state-memDCDC_REG3 vvcc_ddrregulator-state-memDCDC_REG4 12ZI2Zvvcc_3v3regulator-state-mem2ZLDO_REG1 1w@Iw@ vcca1v8_pmuMregulator-state-memw@LDO_REG2 1 I  vdda_0v9regulator-state-memLDO_REG3 1 I  vdda0v9_pmuregulator-state-mem LDO_REG4 12ZI2Z vccio_acodecregulator-state-memLDO_REG5 1w@I2Z vccio_sdregulator-state-memLDO_REG6 12ZI2Z vcc3v3_pmuregulator-state-mem2ZLDO_REG7 1w@Iw@vcc_1v8regulator-state-memLDO_REG8 1w@I2Z vcc1v8_dvpregulator-state-memLDO_REG9 1*I* vcc2v8_dvpregulator-state-memBOOST 1G`IReboost%regulator-state-memOTG_SWITCH otg_switchregulator-state-memcharger&'Dregulator@40 ,fcs,fan53555@k 1 4I5vdd_cpua$regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Vt  ,baudclkapb_pclk''(default Edisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk)defaultEokaypwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*default Edisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm   0 pwmpclk+default Edisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0  0 pwmpclk,default Edisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@7 -power-domain@8  ./0power-domain@9   123power-domain@10  456789power-domain@11  :power-domain@13  ;power-domain@14  <=>power-domain@15 ?@ABCgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$V()' jobmmugpu gpubusEokayDEvideo-codec@fdea0400,rockchip,rk3568-vpu Vvdpu  aclkhclkF iommu@fdea0800,rockchip,rk3568-iommu@ V aclkiface  Frga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga VZ aclkhclksclk &$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu V@  aclkhclkG iommu@fdee0800,rockchip,rk3568-iommu@ V?  aclkiface Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Vd  biuciuciu-driveciu-sampleр resetEokay*4ERhHsz IJKdefaultLMethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aV macirqeth_wake_irq@ Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref  stmmacethsNOP Edisabledmdio,snps,dwmac-mdio stmmac-axi-configNrx-queues-config.Oqueue0tx-queues-configDPqueue0vop@fe040000 0@Zvopgamma-lut V( %aclkhclkdclk_vp0dclk_vp1dclk_vp2Q sEokay,rockchip,rk3566-vop7\ports port@0 endpoint@2dRZport@1 endpoint@4dSUport@2 iommu@fe043e00,rockchip,rk3568-iommu >? V  aclkiface EokayQdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi VDpclk dphyT apb sEokayports port@0endpointdUSport@1endpointdVdsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi VEpclk dphyW apb s Edisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  V-( (iahbisfrcecrefdefaultX sEokaytYports port@0endpointdZRport@1endpointd[qos@fe128000,rockchip,rk3568-qossyscon -qos@fe138080,rockchip,rk3568-qossyscon <qos@fe138100,rockchip,rk3568-qossyscon =qos@fe138180,rockchip,rk3568-qossyscon >qos@fe148000,rockchip,rk3568-qossyscon .qos@fe148080,rockchip,rk3568-qossyscon /qos@fe148100,rockchip,rk3568-qossyscon 0qos@fe150000,rockchip,rk3568-qossyscon :qos@fe158000,rockchip,rk3568-qossyscon 4qos@fe158100,rockchip,rk3568-qossyscon 5qos@fe158180,rockchip,rk3568-qossyscon 6qos@fe158200,rockchip,rk3568-qossyscon 7qos@fe158280,rockchip,rk3568-qossyscon 8qos@fe158300,rockchip,rk3568-qossyscon 9qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon ?qos@fe190280,rockchip,rk3568-qossyscon @qos@fe190300,rockchip,rk3568-qossyscon Aqos@fe190380,rockchip,rk3568-qossyscon Bqos@fe190400,rockchip,rk3568-qossyscon Cqos@fe198000,rockchip,rk3568-qossyscon ;qos@fe1a8000,rockchip,rk3568-qossyscon 1qos@fe1a8080,rockchip,rk3568-qossyscon 2qos@fe1a8100,rockchip,rk3568-qossyscon 3dfi@fe230000,rockchip,rk3568-dfi# V \pcie@fe260000,rockchip,rk3568-pcie0@&Zdbiapbconfig<VKJIHGsyspmcmsglegacyerr( $aclk_mstaclk_slvaclk_dbipclkauxpcij`]]]]^ pcie-phyTt @@ pipe  Edisabledlegacy-interrupt-controllerjU VH]mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Vb  biuciuciu-driveciu-sampleр resetEokay*4 ! _`abdefault mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Vc  biuciuciu-driveciu-sampleр resetEokay*4 c  defgdefault spi@fe300000 ,rockchip,sfc0@ Ve xvclk_sfchclk_sfchdefault Edisabledmmc@fe310000,rockchip,rk3568-dwcmshc1 V7{}G n6( |zy{}corebusaxiblocktimer Edisabledrng@fe388000,rockchip,rk3568-rng8@ po coreahb m Edisabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ V47=AGFqFq ?C9mclk_txmclk_rxhclki *tx PQ tx-mrx-msEokay i2s@fe410000,rockchip,rk3568-i2s-tdmA V57EIGFqFq GK:mclk_txmclk_rxhclkii *rxtx RS tx-mrx-msdefaultjklmEokay 4i2s@fe420000,rockchip,rk3568-i2s-tdmB V67MGFq OO;mclk_txmclk_rxhclkii *txrx Ttx-msdefaultnopq Edisabledi2s@fe430000,rockchip,rk3568-i2s-tdmC V7 SW<mclk_txmclk_rxhclkii *txrx UV tx-mrx-ms Edisabledpdm@fe440000,rockchip,rk3568-pdmD VL ZYpdm_clkpdm_hclki  *rxrstuvwdefault Xpdm-m Edisabledspdif@fe460000,rockchip,rk3568-spdifF Vf mclkhclk _\i *txdefaultx Edisableddma-controller@fe530000,arm,pl330arm,primecellS@V  O   apb_pclk f'dma-controller@fe550000,arm,pl330arm,primecellU@V O   apb_pclk fii2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ V/ HG i2cpclkydefault  Edisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ V0 JI i2cpclkzdefault  Edisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ V1 LK i2cpclk{default  Edisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] V2 NM i2cpclk|default  Edisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ V3 PO i2cpclk}default EokayYwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` V  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia Vg RQspiclkapb_pclk'' *txrxdefault ~  Edisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib Vh TSspiclkapb_pclk'' *txrxdefault   Edisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic Vi VUspiclkapb_pclk'' *txrxdefault   Edisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid Vj XWspiclkapb_pclk'' *txrxdefault   Edisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Vu baudclkapb_pclk'' defaultEokay qbluetooth*,realtek,rtl8821cs-btrealtek,rtl8723bs-bt   serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Vv # baudclkapb_pclk''defaultEokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Vw '$baudclkapb_pclk''default Edisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Vx +(baudclkapb_pclk'' default Edisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Vy /,baudclkapb_pclk' ' default Edisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Vz 30baudclkapb_pclk' ' default Edisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk V{ 74baudclkapb_pclk''default Edisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl V| ;8baudclkapb_pclk''default Edisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm V} ?<baudclkapb_pclk''default Edisabledthermal-zonescpu-thermal d  tripscpu_alert0 p ?passivecpu_alert1 $ ?passivecpu_crit s  ?criticalcooling-mapsmap0 0 gpu-thermal   tripsgpu-threshold p ?passivegpu-target $ ?passivegpu-crit s  ?criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq Vs7Gf@ ` tsadcapb_pclk s sdefaultsleep & 0Eokay F ]saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr V] saradcapb_pclk  saradc-apb xEokay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault Edisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultEokaypwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn  ZY pwmpclkdefaultEokaypwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0 ZY pwmpclkdefaultEokaypwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault Edisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault Edisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo  ]\ pwmpclkdefault Edisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0 ]\ pwmpclkdefault Edisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault Edisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault Edisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp  `_ pwmpclkdefault Edisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0 `_ pwmpclkdefault Edisabledphy@fe830000,rockchip,rk3568-naneng-combphy "} refapbpipe7"G phy   Eokayphy@fe840000,rockchip,rk3568-naneng-combphy %~ refapbpipe7%G phy    Edisabledphy@fe870000,rockchip,rk3568-csi-dphy ypclk  apbs Edisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclk z  apb EokayTmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk {  apb  EdisabledWusb2phy@fe8a0000,rockchip,rk3568-usb2phy phyclkclk_usbphy0_480m V Eokayhost-port  Edisabledotg-port Eokayusb2phy@fe8b0000,rockchip,rk3568-usb2phy phyclkclk_usbphy1_480m V Eokayhost-port Eokayotg-port  Edisabledpinctrl,rockchip,rk3568-pinctrls\ tgpio@fdd60000,rockchip,gpio-bank V! .    Uj!gpio@fe740000,rockchip,gpio-bankt V" cd   Ujgpio@fe750000,rockchip,gpio-banku V# ef  @  Ujcgpio@fe760000,rockchip,gpio-bankv V$ gh  `  Ujgpio@fe770000,rockchip,gpio-bankw V% ij   Ujpcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  *pcfg-output-low ?acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 Jcpuebcedpdpemmceth0eth1flashfspifspi-pins` Jhgmac0gmac1gpuhdmitxhdmitxm0-cec JXi2c0i2c0-xfer J   i2c1i2c1-xfer J  yi2c2i2c2m0-xfer J zi2c3i2c3m0-xfer J{i2c4i2c4m0-xfer J  |i2c5i2c5m1-xfer J}i2s1i2s1m0-lrcktx Jki2s1m0-mclk J"i2s1m0-sclktx Jji2s1m0-sdi0 J li2s1m0-sdo0 Jmi2s2i2s2m0-lrcktx Joi2s2m0-sclktx Jni2s2m0-sdi Jpi2s2m0-sdo Jqi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Jrpdmm0-clk1 Jspdmm0-sdi0 J tpdmm0-sdi1 J updmm0-sdi2 J vpdmm0-sdi3 Jwpmicpmic-int-l J#pmupwm0pwm0m1-pins J)pwm1pwm1m0-pins J*pwm2pwm2m0-pins J+pwm3pwm3-pins J,pwm4pwm4-pins Jpwm5pwm5-pins Jpwm6pwm6-pins Jpwm7pwm7-pins Jpwm8pwm8m0-pins J pwm9pwm9m0-pins J pwm10pwm10m0-pins J pwm11pwm11m0-pins Jpwm12pwm12m0-pins Jpwm13pwm13m0-pins Jpwm14pwm14m0-pins Jpwm15pwm15m0-pins Jrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ J_sdmmc0-clk J`sdmmc0-cmd Jasdmmc0-det Jbsdmmc1sdmmc1-bus4@ Jdsdmmc1-clk Jfsdmmc1-cmd Jesdmmc1-det J gsdmmc2sdmmc2m0-bus4@ JIsdmmc2m0-clk JKsdmmc2m0-cmd JJspdifspdifm0-tx Jxspi0spi0m0-pins0 J spi0m0-cs0 J~spi0m0-cs1 Jspi1spi1m0-pins0 J spi1m0-cs0 Jspi1m0-cs1 Jspi2spi2m0-pins0 Jspi2m0-cs0 Jspi2m0-cs1 Jspi3spi3m0-pins0 J  spi3m0-cs0 Jspi3m0-cs1 Jtsadctsadc-shutorg Jtsadc-pin Juart0uart0-xfer J(uart1uart1m1-xfer Juart1m1-ctsn Juart1m1-rtsn Juart2uart2m0-xfer Juart3uart3m0-xfer Juart4uart4m0-xfer Juart5uart5m0-xfer Juart6uart6m0-xfer Juart7uart7m0-xfer Juart8uart8m0-xfer Juart9uart9m0-xfer Jvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2gpio-btnsbtn-pins-ctrl J     btn-pins-vol Jjoy-muxjoy-mux-en J sdio-pwrseqwifi-enable-h Jvcc3v3-lcdvcc-lcd-h Jvcc-wifivcc-wifi-h Jaudio-amplifierspk-amp-enable-h Jgpio-lcdlcd-reset Jgpio-spispi-pins0 J opp-table-0,operating-points-v2 Xopp-408000000 cQ j P P0 x@opp-600000000 c#F j P P0 x@opp-816000000 c0, j P P0 x@ opp-1104000000 cAʹ j 0 x@opp-1416000000 cTfr j0 x@opp-1608000000 c_" j0 x@opp-1800000000 ckI j000 x@opp-table-1,operating-points-v2Dopp-200000000 c  j P PB@opp-300000000 c j P PB@opp-400000000 cׄ j P PB@opp-600000000 c#F j B@opp-700000000 c)' j~~B@opp-800000000 c/ jB@B@B@chosen serial2:1500000n8adc-keys ,adc-keys  buttons w@ <button-mode MODE < gpio-keys-control ,gpio-keysdefaultbutton-b  SOUTH 0button-down  DPAD-DOWN !button-l1  TL 6button-l2  TL2 8button-select  SELECT :button-start  START ;button-up  DPAD-UP  button-x  NORTH 3button-a  EAST 1button-left  DPAD-LEFT "button-right  DPAD-RIGHT #button-r1  TR 7button-r2  TR2 9button-thumbl  THUMBL =button-thumbr  THUMBR >button-y  WEST 4gpio-keys-vol ,gpio-keys defaultbutton-vol-down  VOLUMEDOWN rbutton-vol-up  VOLUMEUP shdmi-con,hdmi-connectortY?cportendpointd[pwm-leds ,pwm-ledsled-0  "on 0power 9 Haled-1  0charging 9 Haled-2  "off 0status 9 Hasdio-pwrseq,mmc-pwrseq-simple  ext_clockdefault M dHregulator-vcc3v3-lcd0,regulator-fixed p! udefault12ZI2Zvcc3v3_lcd0_nregulator-state-memregulator-vcc-sys,regulator-fixed 19I9vcc_sys$regulator-vcc-wifi,regulator-fixed u p!default 12ZI2Z vcc_wifiLpwm-vibrator ,pwm-vibrator enable H;adc-joystick ,adc-joystick default < axis@0    axis@1    axis@2    axis@3    adc-mux,io-channel-mux left_xright_xleft_yright_y x  parent  dbattery,simple-battery 4   .@@ T {? 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