u8( ɴ ,radxa,zero-3wrockchip,rk35667Radxa ZERO 3Waliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe310000/mmc@fe2b0000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55psci -@?LY@kx cpu@100cpu,arm,cortex-a55psci -@?LY@kx cpu@200cpu,arm,cortex-a55psci -@?LY@kx cpu@300cpu,arm,cortex-a55psci -@?LY@kx l3-cache,cache"/@Adisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smcЂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s8okaysimple-audio-card,codec?simple-audio-card,cpu? pmu,arm,cortex-a55-pmu0IT psci ,arm,psci-1.0smcreserved-memory gshmem@10f000,arm,scmi-shmemntimer,arm,armv8-timer0I   uxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob I_ sata-phy 8disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob I` sata-phy 8disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Iref_clksuspend_clkbus_clkotg  utmi_wide8okay usb2-phy3 :high-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Iref_clksuspend_clkbus_clkhost usb2-phyusb3-phy  utmi_wide8okayinterrupt-controller@fd400000 ,arm,gic-v3 @F I H]nAx(g msi-controller@fd440000,arm,gic-v3-itsDWusb@fd800000 ,generic-ehci Iusb 8disabledusb@fd840000 ,generic-ohci Iusb 8disabledusb@fd880000 ,generic-ehci Iusb 8disabledusb@fd8c0000 ,generic-ohci Iusb 8disabledsyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdUio-domains&,rockchip,rk3568-pmu-io-voltage-domain8okaysyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru+clock-controller@fdd20000,rockchip,rk3568-cruxin24m+8 HG ]t i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c I.- i2cpclk!default 8okaypmic@20,rockchip,rk817 rk817-clkout1rk817-clkout2"Idefault#$$$$$$$$%regulatorsDCDC_REG1 vdd_logic"6H_ wpqregulator-state-mem DCDC_REG2 vdd_gpu_npu"6H_ wpqDregulator-state-memDCDC_REG3vcc_ddr"6Hregulator-state-memDCDC_REG4 vcc3v3_sys"6H_2Zw2Z\regulator-state-mem2ZLDO_REG1 vcca1v8_pmu"6_w@ww@regulator-state-memw@LDO_REG2 vdda_0v9"6_ w Qregulator-state-memLDO_REG3 vdda0v9_pmu"6_ w regulator-state-mem LDO_REG4 vccio_acodec"6_2Zw2Zregulator-state-memLDO_REG5 vccio_sd"6_w@w2Zregulator-state-memLDO_REG6 vcc3v3_pmu"6_2Zw2Zregulator-state-mem2ZLDO_REG7 vcc_1v8_p"6_w@ww@regulator-state-memLDO_REG8 vcc1v8_dvp"6_w@ww@regulator-state-memLDO_REG9 vcc2v8_dvp"6_*w*regulator-state-memBOOST vcc5v_midu"6_LK@wLK@%regulator-state-memOTG_SWITCHvbusregulator-state-memregulator@40,rockchip,rk8600@vdd_cpu"6_ 4w5$regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart It ,baudclkapb_pclk&&'default+ 8disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(default5 8disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)default5 8disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*default5 8disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk+default5 8disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller@ power-domain@7T,@power-domain@8 T-./@power-domain@9  T012@power-domain@10 T345678@power-domain@11 T9@power-domain@13 T:@power-domain@14 T;<=@power-domain@15T>?@AB@gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$I()' [jobmmugpugpubus8okayCkDvideo-codec@fdea0400,rockchip,rk3568-vpu I[vdpu aclkhclkwE iommu@fdea0800,rockchip,rk3568-iommu@ I aclkiface ~Erga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga IZaclkhclksclk&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu I@ aclkhclkwF iommu@fdee0800,rockchip,rk3568-iommu@ I? aclkiface ~Fmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Id biuciuciu-driveciu-sampleрreset 8disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aI [macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref stmmacetht GHI 8disabledmdio,snps,dwmac-mdio stmmac-axi-config Grx-queues-config*Hqueue0tx-queues-config@Iqueue0vop@fe040000 0@Vvopgamma-lut I(%aclkhclkdclk_vp0dclk_vp1dclk_vp2wJ t 8okay,rockchip,rk3566-vop8]ports port@0 endpoint@2`KSport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? I aclkiface~ 8okayJdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi IDpclkdphyL apbt  8disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi IEpclkdphyM apbt  8disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  I-((iahbisfrcecrefdefault NOP t p8okayQRports port@0endpoint`SKport@1endpoint`Tqos@fe128000,rockchip,rk3568-qossyscon ,qos@fe138080,rockchip,rk3568-qossyscon ;qos@fe138100,rockchip,rk3568-qossyscon <qos@fe138180,rockchip,rk3568-qossyscon =qos@fe148000,rockchip,rk3568-qossyscon -qos@fe148080,rockchip,rk3568-qossyscon .qos@fe148100,rockchip,rk3568-qossyscon /qos@fe150000,rockchip,rk3568-qossyscon 9qos@fe158000,rockchip,rk3568-qossyscon 3qos@fe158100,rockchip,rk3568-qossyscon 4qos@fe158180,rockchip,rk3568-qossyscon 5qos@fe158200,rockchip,rk3568-qossyscon 6qos@fe158280,rockchip,rk3568-qossyscon 7qos@fe158300,rockchip,rk3568-qossyscon 8qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon >qos@fe190280,rockchip,rk3568-qossyscon ?qos@fe190300,rockchip,rk3568-qossyscon @qos@fe190380,rockchip,rk3568-qossyscon Aqos@fe190400,rockchip,rk3568-qossyscon Bqos@fe198000,rockchip,rk3568-qossyscon :qos@fe1a8000,rockchip,rk3568-qossyscon 0qos@fe1a8080,rockchip,rk3568-qossyscon 1qos@fe1a8100,rockchip,rk3568-qossyscon 2dfi@fe230000,rockchip,rk3568-dfi# I Upcie@fe260000,rockchip,rk3568-pcie0@&Vdbiapbconfig<IKJIHG[syspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpci]`VVVVW pcie-phyTg @@pipe  8disabledlegacy-interrupt-controller]H IHVmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Ib biuciuciu-driveciu-sampleрreset8okay)3DdefaultXYZ[O\[mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Ic biuciuciu-driveciu-sampleрreset8okay)3hu]default ^_`O[spi@fe300000 ,rockchip,sfc0@ Iexvclk_sfchclk_sfcadefault 8disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 I8{}H n6(|zy{}corebusaxiblocktimer8okay) defaultbcdeO[rng@fe388000,rockchip,rk3568-rng8@po coreahbm 8disabledi2s@fe400000,rockchip,rk3568-i2s-tdm@ I48=AHFqFq?C9mclk_txmclk_rxhclkftxPQ tx-mrx-mt p8okay i2s@fe410000,rockchip,rk3568-i2s-tdmA I58EIHFqFqGK:mclk_txmclk_rxhclkffrxtxRS tx-mrx-mt default0ghijklmnopqrp 8disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB I68MHFqOO;mclk_txmclk_rxhclkfftxrxTtx-mt defaultstuvp 8disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC I7SW<mclk_txmclk_rxhclkfftxrxUV tx-mrx-mt p 8disabledpdm@fe440000,rockchip,rk3568-pdmD ILZYpdm_clkpdm_hclkf rxwxyz{|defaultXpdm-mp 8disabledspdif@fe460000,rockchip,rk3568-spdifF If mclkhclk_\ftxdefault}p 8disableddma-controller@fe530000,arm,pl330arm,primecellS@I   apb_pclk &dma-controller@fe550000,arm,pl330arm,primecellU@I  apb_pclk fi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ I/HG i2cpclk~default  8disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ I0JI i2cpclkdefault  8disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ I1LK i2cpclkdefault  8disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] I2NM i2cpclkdefault  8disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ I3PO i2cpclkdefault  8disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` I tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia IgRQspiclkapb_pclk&&txrxdefault   8disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib IhTSspiclkapb_pclk&&txrxdefault   8disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic IiVUspiclkapb_pclk&&txrxdefault   8disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid IjXWspiclkapb_pclk&&txrxdefault   8disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Iubaudclkapb_pclk&& default+8okay serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Iv# baudclkapb_pclk&&default+8okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Iw'$baudclkapb_pclk&&default+ 8disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Ix+(baudclkapb_pclk&& default+ 8disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Iy/,baudclkapb_pclk& & default+ 8disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Iz30baudclkapb_pclk& & default+ 8disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk I{74baudclkapb_pclk&&default+ 8disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl I|;8baudclkapb_pclk&&default+ 8disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm I}?<baudclkapb_pclk&&default+ 8disabledthermal-zonescpu-thermal $d : Htripscpu_alert0 Xp dpassivecpu_alert1 X$ dpassivecpu_crit Xs d criticalcooling-mapsmap0 o0 t gpu-thermal $ : Htripsgpu-threshold Xp dpassivegpu-target X$ dpassivegpu-crit Xs d criticalcooling-mapsmap0 o ttsadc@fe710000,rockchip,rk3568-tsadcq Is8Hf@ `tsadcapb_pclkt  sdefaultsleep  8okay  saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr I]saradcapb_pclk saradc-apb 8okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault5 8disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault5 8disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault5 8disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault5 8disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault5 8disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault5 8disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault5 8disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault5 8disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault5 8disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault5 8disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault5 8disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault5 8disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe8"Hphy   28okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe8%Hphy   2 8disabledphy@fe870000,rockchip,rk3568-csi-dphyypclk 2apbt  8disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz 2 apb 8disabledLmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ 2 apb 8disabledMusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m I =8okayhost-port 28okayotg-port 28okayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m I = 8disabledhost-port 2 8disabledotg-port 2 8disabledpinctrl,rockchip,rk3568-pinctrlt U ggpio@fdd60000,rockchip,gpio-bank I!.  M ]  iH]B upin-10 [GPIO0_D0]pin-08 [GPIO0_D1]"gpio@fe740000,rockchip,gpio-bankt I"cd M ]  iH]S upin-03 [GPIO1_A0]pin-05 [GPIO1_A1]pin-37 [GPIO1_A4]gpio@fe750000,rockchip,gpio-banku I#ef M ]@  iH] ugpio@fe760000,rockchip,gpio-bankv I$gh M ]`  iH]0 upin-11 [GPIO3_A1]pin-13 [GPIO3_A2]pin-12 [GPIO3_A3]pin-35 [GPIO3_A4]pin-40 [GPIO3_A5]pin-38 [GPIO3_A6]pin-36 [GPIO3_A7]pin-15 [GPIO3_B0]pin-16 [GPIO3_B1]pin-18 [GPIO3_B2]pin-29 [GPIO3_B3]pin-31 [GPIO3_B4]pin-22 [GPIO3_C1]pin-32 [GPIO3_C2]pin-33 [GPIO3_C3]pin-07 [GPIO3_C4]gpio@fe770000,rockchip,gpio-bankw I%ij M ]  iH] upin-27 [GPIO4_B2]pin-28 [GPIO4_B3]pin-23 [GPIO4_C2]pin-19 [GPIO4_C3]pin-21 [GPIO4_C5]pin-24 [GPIO4_C6]pcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   bemmc-clk cemmc-cmd demmc-datastrobe eeth0eth1flashfspifspi-pins` agmac0gmac1gpuhdmitxhdmitxm0-cec Phdmitx-scl Nhdmitx-sda Oi2c0i2c0-xfer  !i2c1i2c1-xfer  ~i2c2i2c2m0-xfer i2c3i2c3m0-xfer i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrckrx ji2s1m0-lrcktx ii2s1m0-sclkrx hi2s1m0-sclktx gi2s1m0-sdi0  ki2s1m0-sdi1  li2s1m0-sdi2  mi2s1m0-sdi3 ni2s1m0-sdo0 oi2s1m0-sdo1 pi2s1m0-sdo2  qi2s1m0-sdo3  ri2s2i2s2m0-lrcktx ti2s2m0-sclktx si2s2m0-sdi ui2s2m0-sdo vi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk wpdmm0-clk1 xpdmm0-sdi0  ypdmm0-sdi1  zpdmm0-sdi2  {pdmm0-sdi3 |pmicpmic-int-l #pmupwm0pwm0m0-pins (pwm1pwm1m0-pins )pwm2pwm2m0-pins *pwm3pwm3-pins +pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ Xsdmmc0-clk Ysdmmc0-cmd Zsdmmc0-det [sdmmc1sdmmc1-bus4@ ^sdmmc1-clk _sdmmc1-cmd `sdmmc2spdifspdifm0-tx }spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer 'uart1uart1m0-xfer   uart1m0-ctsn uart1m0-rtsn  uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsuser-led2 bluetoothbt-reg-on-h bt-wake-host-h host-wake-bt-h wifiwifi-reg-on-h wifi-wake-host-h opp-table-0,operating-points-v2 opp-408000000 Q P P0 @opp-600000000 #F P P0 @opp-816000000 0, P P0 @ opp-1104000000 Aʹ 0 @opp-1416000000 Tfr 0 @opp-table-1,operating-points-v2Copp-200000000  P PB@opp-300000000  P PB@opp-400000000 ׄ P PB@opp-600000000 #F B@opp-700000000 )' ~~B@chosen serial2:1500000n8hdmi-con,hdmi-connectordportendpoint`Tleds ,gpio-ledsdefaultled-green  on .heartbeat 7" =heartbeatregulator-1v8-vcc,regulator-fixedvcc_1v8"6_w@ww@regulator-1v8-vcca,regulator-fixed vcca_1v8"6_w@ww@regulator-1v8-vcca-image,regulator-fixedvcca1v8_image"6_w@ww@Rregulator-3v3-vcc,regulator-fixedvcc_3v3"6_2Zw2Z\regulator-5v0-vcc-sys,regulator-fixedvcc_sys"6_LK@wLK@$sdio-pwrseq,mmc-pwrseq-simple ext_clockdefault Sd jLK@ }"] interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grfsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-initial-moderegulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-suspend-microvoltregulator-on-in-suspendfcs,suspend-voltage-selectorvin-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesbus-widthcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-mmcno-sdnon-removablesd-uhs-sdr104cap-mmc-highspeedmmc-hs200-1_8vno-sdiodma-namesarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsgpio-line-namesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendstdout-pathcolordefault-statefunctiongpioslinux,default-triggerpost-power-on-delay-mspower-off-delay-usreset-gpios