8( K ',friendlyarm,nanopi-r5crockchip,rk35687FriendlyElec NanoPi R5Caliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe2b0000/mmc@fe310000cpus cpu@0cpu,arm,cortex-a55 psci(@:GT@fs cpu@100cpu,arm,cortex-a55 psci(@:GT@fs cpu@200cpu,arm,cortex-a55 psci(@:GT@fs cpu@300cpu,arm,cortex-a55 psci(@:GT@fs l3-cache,cache*@<display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc˂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s3okaysimple-audio-card,codec:simple-audio-card,cpu: pmu,arm,cortex-a55-pmu0DO psci ,arm,psci-1.0smcreserved-memory bshmem@10f000,arm,scmi-shmemitimer,arm,armv8-timer0D   pxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob D_ sata-phy 3disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob D` sata-phy 3disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Dref_clksuspend_clkbus_clkhost utmi_wide3okay usb2-phyusb3-phy.usb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Dref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide3okayinterrupt-controller@fd400000 ,arm,gic-v3 @F D 5J[Ae(pb msi-controller@fd440000,arm,gic-v3-itsDpZusb@fd800000 ,generic-ehci Dusb3okayusb@fd840000 ,generic-ohci Dusb3okayusb@fd880000 ,generic-ehci Dusb3okayusb@fd8c0000 ,generic-ohci Dusb3okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdXio-domains&,rockchip,rk3568-pmu-io-voltage-domain3okaysyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru clock-controller@fdd20000,rockchip,rk3568-cruxin24m  'G <S i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c D.- i2cpclk!default 3okayregulator@1c ,tcs,tcs4525`}vdd_cpu 50"regulator-state-mempmic@20,rockchip,rk809 #Ddefault$3%?%K%W%c%o%{%%%regulatorsDCDC_REG1 }vdd_logic pqregulator-state-memDCDC_REG2}vdd_gpu pqGregulator-state-memDCDC_REG3}vcc_ddrregulator-state-memDCDC_REG4}vdd_npu pqregulator-state-memDCDC_REG5}vcc_1v8w@w@regulator-state-memLDO_REG1}vdda0v9_image~~Tregulator-state-memLDO_REG2 }vdda_0v9  regulator-state-memLDO_REG3 }vdda0v9_pmu  regulator-state-mem LDO_REG4 }vccio_acodec2Z2Zregulator-state-memLDO_REG5 }vccio_sdw@2Zregulator-state-memLDO_REG6 }vcc3v3_pmu2Z2Zregulator-state-mem2ZLDO_REG7 }vcca_1v8w@w@regulator-state-memLDO_REG8 }vcca1v8_pmuw@w@regulator-state-memw@LDO_REG9}vcca1v8_imagew@w@Uregulator-state-memSWITCH_REG1}vcc_3v3regulator-state-memSWITCH_REG2 }vcc3v3_sd]regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Dt ,baudclkapb_pclk&&'default  3disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(default 3disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)default 3disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*default 3disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk+default 3disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@73,power-domain@8 3-./power-domain@9  3012power-domain@10 3345678power-domain@11 39power-domain@13 3:power-domain@14 3;<=power-domain@15 3>?@ABCDEgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$D()' :jobmmugpugpubus3okayFJGvideo-codec@fdea0400,rockchip,rk3568-vpu D:vdpu aclkhclkVH iommu@fdea0800,rockchip,rk3568-iommu@ D aclkiface ]Hrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga DZaclkhclksclk&$% jcoreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu D@ aclkhclkVI iommu@fdee0800,rockchip,rk3568-iommu@ D? aclkiface ]Immc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Dd biuciuciu-driveciu-samplevрjreset 3disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aD :macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref jstmmacethS JKL 3disabledmdio,snps,dwmac-mdio stmmac-axi-configJrx-queues-config Kqueue0tx-queues-configLqueue0vop@fe040000 0@5vopgamma-lut D(%aclkhclkdclk_vp0dclk_vp1dclk_vp2VM S 3okay,rockchip,rk3568-vop<ports port@0 endpoint@2?NVport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? D aclkiface] 3okayMdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DDpclkdphyO japbS  3disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DEpclkdphyP japbS  3disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  D-((iahbisfrcecrefdefault QRS S O3okay`TpUports port@0endpoint?VNport@1endpoint?Wqos@fe128000,rockchip,rk3568-qossyscon ,qos@fe138080,rockchip,rk3568-qossyscon ;qos@fe138100,rockchip,rk3568-qossyscon <qos@fe138180,rockchip,rk3568-qossyscon =qos@fe148000,rockchip,rk3568-qossyscon -qos@fe148080,rockchip,rk3568-qossyscon .qos@fe148100,rockchip,rk3568-qossyscon /qos@fe150000,rockchip,rk3568-qossyscon 9qos@fe158000,rockchip,rk3568-qossyscon 3qos@fe158100,rockchip,rk3568-qossyscon 4qos@fe158180,rockchip,rk3568-qossyscon 5qos@fe158200,rockchip,rk3568-qossyscon 6qos@fe158280,rockchip,rk3568-qossyscon 7qos@fe158300,rockchip,rk3568-qossyscon 8qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon >qos@fe190280,rockchip,rk3568-qossyscon Bqos@fe190300,rockchip,rk3568-qossyscon Cqos@fe190380,rockchip,rk3568-qossyscon Dqos@fe190400,rockchip,rk3568-qossyscon Eqos@fe198000,rockchip,rk3568-qossyscon :qos@fe1a8000,rockchip,rk3568-qossyscon 0qos@fe1a8080,rockchip,rk3568-qossyscon 1qos@fe1a8100,rockchip,rk3568-qossyscon 2dfi@fe230000,rockchip,rk3568-dfi# D Xpcie@fe260000,rockchip,rk3568-pcie0@&5dbiapbconfig<DKJIHG:syspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpciJ`YYYYZ pcie-phyTb @@jpipe 3okaydefault[ \legacy-interrupt-controllerJ5 DHYmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Db biuciuciu-driveciu-samplevрjreset3okay#-?P[]gdefault^_`ammc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Dc biuciuciu-driveciu-samplevрjreset 3disabledspi@fe300000 ,rockchip,sfc0@ Dexvclk_sfchclk_sfcbdefault 3disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 D{}' n6(|zy{}corebusaxiblocktimer3okay# tdefaultcdef[grng@fe388000,rockchip,rk3568-rng8@po coreahbm3okayi2s@fe400000,rockchip,rk3568-i2s-tdm@ D4=A'FqFq?C9mclk_txmclk_rxhclkgtxPQ jtx-mrx-mS O3okay i2s@fe410000,rockchip,rk3568-i2s-tdmA D5EI'FqFqGK:mclk_txmclk_rxhclkggrxtxRS jtx-mrx-mS default0hijklmnopqrsO 3disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB D6M'FqOO;mclk_txmclk_rxhclkggtxrxTjtx-mS defaulttuvwO 3disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC D7SW<mclk_txmclk_rxhclkggtxrxUV jtx-mrx-mS O 3disabledpdm@fe440000,rockchip,rk3568-pdmD DLZYpdm_clkpdm_hclkg rxxyz{|}defaultXjpdm-mO 3disabledspdif@fe460000,rockchip,rk3568-spdifF Df mclkhclk_\gtxdefault~O 3disableddma-controller@fe530000,arm,pl330arm,primecellS@D   apb_pclk&dma-controller@fe550000,arm,pl330arm,primecellU@D  apb_pclkgi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ D/HG i2cpclkdefault  3disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ D0JI i2cpclkdefault  3disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ D1LK i2cpclkdefault  3disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] D2NM i2cpclkdefault  3disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ D3PO i2cpclkdefault 3okayrtc@51,haoyu,hym8563Q#D rtcic_32koutdefaultwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` D tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia DgRQspiclkapb_pclk&&txrxdefault   3disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib DhTSspiclkapb_pclk&&txrxdefault   3disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic DiVUspiclkapb_pclk&&txrxdefault   3disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid DjXWspiclkapb_pclk&&txrxdefault   3disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Dubaudclkapb_pclk&&default  3disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Dv# baudclkapb_pclk&&default 3okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Dw'$baudclkapb_pclk&&default  3disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Dx+(baudclkapb_pclk&& default  3disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Dy/,baudclkapb_pclk& & default  3disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Dz30baudclkapb_pclk& & default  3disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk D{74baudclkapb_pclk&&default  3disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl D|;8baudclkapb_pclk&&default  3disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm D}?<baudclkapb_pclk&&default  3disabledthermal-zonescpu-thermaldtripscpu_alert0ppassivecpu_alert1$passivecpu_crits criticalcooling-mapsmap0 0 gpu-thermaltripsgpu-thresholdppassivegpu-target$passivegpu-crits criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq Ds'f@ `tsadcapb_pclkS  sdefaultsleep 3 =3okay S jsaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr D]saradcapb_pclk jsaradc-apb 3okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault 3disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault 3disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault 3disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault 3disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault 3disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault 3disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault 3disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault 3disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault 3disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault 3disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault 3disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault 3disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe"'jphy   3okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe%'jphy   3okayphy@fe870000,rockchip,rk3568-csi-dphyypclk japbS  3disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz  japb 3disabledOmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{  japb 3disabledPusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m D 3okayhost-port 3okay otg-port 3okayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m D 3okayhost-port 3okay otg-port 3okaypinctrl,rockchip,rk3568-pinctrlS X bgpio@fdd60000,rockchip,gpio-bank D!.     5J#gpio@fe740000,rockchip,gpio-bankt D"cd    5Jgpio@fe750000,rockchip,gpio-banku D#ef  @  5Jgpio@fe760000,rockchip,gpio-bankv D$gh  `  5J\gpio@fe770000,rockchip,gpio-bankw D%ij    5Jpcfg-pull-up pcfg-pull-none &pcfg-pull-none-drv-level-1 & 3pcfg-pull-none-drv-level-2 & 3pcfg-pull-none-drv-level-3 & 3pcfg-pull-up-drv-level-1  3pcfg-pull-up-drv-level-2  3pcfg-pull-none-smt & Bacodecaudiopwmbt656bt1120camcan0can0m0-pins W  can1can1m0-pins Wcan2can2m0-pins W  cifclk32kclk32k-out0 Wcpuebcedpdpemmcemmc-bus8 W  cemmc-clk Wdemmc-cmd Weemmc-datastrobe Wfeth0eth1flashfspifspi-pins` Wbgmac0gmac1gpuhdmitxhdmitxm0-cec WShdmitx-scl WQhdmitx-sda WRi2c0i2c0-xfer W  !i2c1i2c1-xfer W  i2c2i2c2m0-xfer W i2c3i2c3m0-xfer Wi2c4i2c4m0-xfer W  i2c5i2c5m0-xfer W  i2s1i2s1m0-lrckrx Wki2s1m0-lrcktx Wji2s1m0-sclkrx Wii2s1m0-sclktx Whi2s1m0-sdi0 W li2s1m0-sdi1 W mi2s1m0-sdi2 W ni2s1m0-sdi3 Woi2s1m0-sdo0 Wpi2s1m0-sdo1 Wqi2s1m0-sdo2 W ri2s1m0-sdo3 W si2s2i2s2m0-lrcktx Wui2s2m0-sclktx Wti2s2m0-sdi Wvi2s2m0-sdo Wwi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk Wxpdmm0-clk1 Wypdmm0-sdi0 W zpdmm0-sdi1 W {pdmm0-sdi2 W |pdmm0-sdi3 W}pmicpmic-int W$pmupwm0pwm0m0-pins W(pwm1pwm1m0-pins W)pwm2pwm2m0-pins W*pwm3pwm3-pins W+pwm4pwm4-pins Wpwm5pwm5-pins Wpwm6pwm6-pins Wpwm7pwm7-pins Wpwm8pwm8m0-pins W pwm9pwm9m0-pins W pwm10pwm10m0-pins W pwm11pwm11m0-pins Wpwm12pwm12m0-pins Wpwm13pwm13m0-pins Wpwm14pwm14m0-pins Wpwm15pwm15m0-pins Wrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ W^sdmmc0-clk W_sdmmc0-cmd W`sdmmc0-det Wasdmmc1sdmmc2spdifspdifm0-tx W~spi0spi0m0-pins0 W spi0m0-cs0 Wspi0m0-cs1 Wspi1spi1m0-pins0 W spi1m0-cs0 Wspi1m0-cs1 Wspi2spi2m0-pins0 Wspi2m0-cs0 Wspi2m0-cs1 Wspi3spi3m0-pins0 W  spi3m0-cs0 Wspi3m0-cs1 Wtsadctsadc-shutorg Wtsadc-pin Wuart0uart0-xfer W'uart1uart1m0-xfer W  uart2uart2m0-xfer Wuart3uart3m0-xfer Wuart4uart4m0-xfer Wuart5uart5m0-xfer Wuart6uart6m0-xfer Wuart7uart7m0-xfer Wuart8uart8m0-xfer Wuart9uart9m0-xfer Wvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2hym8563hym8563-int Wusbvcc5v0-usb-host-en Wvcc5v0-usb-otg-en Wgpio-ledslan-led-pin Wpower-led-pin Wwan-led-pin Wwlan-led-pin Wpciepcie20-reset-pin W[rockchip-keyreset-button-pin Wopp-table-0,operating-points-v2 eopp-408000000 pQ w P P0 @opp-600000000 p#F w P P0 @opp-816000000 p0, w P P0 @ opp-1104000000 pAʹ w 0 @opp-1416000000 pTfr w0 @opp-1608000000 p_" w0 @opp-1800000000 pkI w000 @opp-1992000000 pv w000 @opp-table-1,operating-points-v2Fopp-200000000 p  w P PB@opp-300000000 p w P PB@opp-400000000 pׄ w P PB@opp-600000000 p#F w B@opp-700000000 p)' w~~B@opp-800000000 p/ wB@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob D^ sata-phy 3disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon ?qos@fe190100,rockchip,rk3568-qossyscon @qos@fe190200,rockchip,rk3568-qossyscon Asyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy &'wrefclk_mrefclk_npclkjphy 3okay pcie@fe270000,rockchip,rk3568-pcie ($aclk_mstaclk_slvaclk_dbipclkauxpci<D:syspmcmsglegacyerrJ`Z pcie-phy0@@'Tb @@@5dbiapbconfigjpipe3okay # legacy-interrupt-controller5J Dpcie@fe280000,rockchip,rk3568-pcie  /($aclk_mstaclk_slvaclk_dbipclkauxpci<D:syspmcmsglegacyerrJ` Z  pcie-phy0@(Tb @@5dbiapbconfigjpipe3okay # legacy-interrupt-controller5J Dethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*D:macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref jstmmacethS  3disabledmdio,snps,dwmac-mdio stmmac-axi-configrx-queues-config queue0tx-queues-configqueue0can@fe570000,rockchip,rk3568v2-canfdW DA@ baudpclkUT jcoreapbdefault 3disabledcan@fe580000,rockchip,rk3568v2-canfdX DCB baudpclkWV jcoreapbdefault 3disabledcan@fe590000,rockchip,rk3568v2-canfdY DED baudpclkYX jcoreapbdefault 3disabledphy@fe820000,rockchip,rk3568-naneng-combphy| refapbpipe'jphy   3okaychosen serial2:1500000n8hdmi-con,hdmi-connectoraportendpoint?Wregulator-vdd-usbc,regulator-fixed }vdd_usbcLK@LK@regulator-vcc3v3-sys,regulator-fixed }vcc3v3_sys2Z2Z%regulator-vcc5v0-sys,regulator-fixed }vcc5v0_sysLK@LK@"regulator-vcc3v3-pcie,regulator-fixed }vcc3v3_pcie2Z2Z  #  @"regulator-vcc5v0-usb,regulator-fixed }vcc5v0_usbLK@LK@regulator-vcc5v0-usb-host,regulator-fixed  #default}vcc5v0_usb_hostLK@LK@regulator-vcc5v0-usb-otg,regulator-fixed  #default}vcc5v0_usb_otgLK@LK@regulator-pcie30-avdd0v9,regulator-fixed}pcie30_avdd0v9  %regulator-pcie30-avdd1v8,regulator-fixed}pcie30_avdd1v8w@w@%gpio-keys ,gpio-keysdefaultbutton-reset 2 # reset gpio-leds ,gpio-ledsdefaultled-lan & ,lan \led-power & ,power 5heartbeat \led-wan & ,wan \led-wlan & ,wlan \ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfphy-supplygpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesvpcie3v3-supplystdout-pathenable-active-highstartup-delay-usgpiodebounce-intervallabellinux,codecolorfunctionlinux,default-trigger