8( ` %,radxa,e25radxa,cm3irockchip,rk35687Radxa E25 Carrier Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe310000/mmc@fe2b0000cpus cpu@0cpu,arm,cortex-a55 psci(@:GT@fs cpu@100cpu,arm,cortex-a55 psci(@:GT@fs cpu@200cpu,arm,cortex-a55 psci(@:GT@fs cpu@300cpu,arm,cortex-a55 psci(@:GT@fs l3-cache,cache*@<display-subsystem,rockchip,display-subsystem disabledfirmwarescmi ,arm,scmi-smc҂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s  disabledsimple-audio-card,codec:simple-audio-card,cpu: pmu,arm,cortex-a55-pmu0DO psci ,arm,psci-1.0smcreserved-memory bshmem@10f000,arm,scmi-shmemitimer,arm,armv8-timer0D   pxin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob D_ sata-phyokaysata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob D` sata-phy disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Dref_clksuspend_clkbus_clkotg utmi_wideokay usb2-phyusb3-phy.usb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Dref_clksuspend_clkbus_clkhost usb2-phyusb3-phy utmi_wide disabledinterrupt-controller@fd400000 ,arm,gic-v3 @F D 5J[Ae(pb msi-controller@fd440000,arm,gic-v3-itsDpUusb@fd800000 ,generic-ehci Dusbokayusb@fd840000 ,generic-ohci Dusbokayusb@fd880000 ,generic-ehci Dusbokayusb@fd8c0000 ,generic-ohci Dusbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdSio-domains&,rockchip,rk3568-pmu-io-voltage-domainokay syscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucruclock-controller@fdd20000,rockchip,rk3568-cruxin24m% 5G Ja i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c D.- i2cpclk!default okayregulator@1c ,tcs,tcs4525nvdd_cpu 50"regulator-state-mempmic@20,rockchip,rk809 #Ddefault$)AO%[%g%s%%%%%%regulatorsDCDC_REG1 vdd_logic pqregulator-state-memDCDC_REG2vdd_gpu pqGregulator-state-memDCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu pqregulator-state-memDCDC_REG5vcc_1v8w@w@regulator-state-memLDO_REG1vdda0v9_image  regulator-state-memLDO_REG2 vdda_0v9  regulator-state-memLDO_REG3 vdda0v9_pmu  regulator-state-mem LDO_REG4 vccio_acodec2Z2Zregulator-state-memLDO_REG5 vccio_sdw@2Zregulator-state-memLDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem2ZLDO_REG7 vcca_1v8w@w@regulator-state-memLDO_REG8 vcca1v8_pmuw@w@regulator-state-memw@LDO_REG9vcca1v8_imagew@w@regulator-state-memSWITCH_REG1vcc_3v3regulator-state-memSWITCH_REG2 vcc3v3_sd\regulator-state-memserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart Dt ,baudclkapb_pclk&&'default  disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(default" disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)default"okaypwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*default"okaypwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk+default" disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller- power-domain@7A,-power-domain@8 A-./-power-domain@9  A012-power-domain@10 A345678-power-domain@11 A9-power-domain@13 A:-power-domain@14 A;<=-power-domain@15 A>?@ABCDE-gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$D()' HjobmmugpugpubusokayFXGvideo-codec@fdea0400,rockchip,rk3568-vpu DHvdpu aclkhclkdH iommu@fdea0800,rockchip,rk3568-iommu@ D aclkiface kHrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga DZaclkhclksclk&$% xcoreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu D@ aclkhclkdI iommu@fdee0800,rockchip,rk3568-iommu@ D? aclkiface kImmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Dd biuciuciu-driveciu-sampleрxreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aD Hmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref xstmmacetha JKL disabledmdio,snps,dwmac-mdio stmmac-axi-configJrx-queues-configKqueue0tx-queues-config-Lqueue0vop@fe040000 0@Cvopgamma-lut D(%aclkhclkdclk_vp0dclk_vp1dclk_vp2dM a  disabled,rockchip,rk3568-vopports port@0 port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? D aclkifacek  disabledMdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DDpclkdphyN xapba  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DEpclkdphyO xapba  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  D-((iahbisfrcecrefdefault PQR  a M disabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon ,qos@fe138080,rockchip,rk3568-qossyscon ;qos@fe138100,rockchip,rk3568-qossyscon <qos@fe138180,rockchip,rk3568-qossyscon =qos@fe148000,rockchip,rk3568-qossyscon -qos@fe148080,rockchip,rk3568-qossyscon .qos@fe148100,rockchip,rk3568-qossyscon /qos@fe150000,rockchip,rk3568-qossyscon 9qos@fe158000,rockchip,rk3568-qossyscon 3qos@fe158100,rockchip,rk3568-qossyscon 4qos@fe158180,rockchip,rk3568-qossyscon 5qos@fe158200,rockchip,rk3568-qossyscon 6qos@fe158280,rockchip,rk3568-qossyscon 7qos@fe158300,rockchip,rk3568-qossyscon 8qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon >qos@fe190280,rockchip,rk3568-qossyscon Bqos@fe190300,rockchip,rk3568-qossyscon Cqos@fe190380,rockchip,rk3568-qossyscon Dqos@fe190400,rockchip,rk3568-qossyscon Eqos@fe198000,rockchip,rk3568-qossyscon :qos@fe1a8000,rockchip,rk3568-qossyscon 0qos@fe1a8080,rockchip,rk3568-qossyscon 1qos@fe1a8100,rockchip,rk3568-qossyscon 2dfi@fe230000,rockchip,rk3568-dfi# D ^Spcie@fe260000,rockchip,rk3568-pcie0@&Cdbiapbconfig<DKJIHGHsyspmcmsglegacyerrk($aclk_mstaclk_slvaclk_dbipclkauxpciJu`TTTTU pcie-phyTb @@xpipe okaydefaultV W Xlegacy-interrupt-controllerJ5 DHTmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Db biuciuciu-driveciu-sampleрxresetokay  #&default YZ[1?\Kmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Dc biuciuciu-driveciu-sampleрxreset disabledspi@fe300000 ,rockchip,sfc0@ Dexvclk_sfchclk_sfc]default disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 D%{}5 n6(|zy{}corebusaxiblocktimerokay Xdefault^_`a?Krng@fe388000,rockchip,rk3568-rng8@po coreahbmokayi2s@fe400000,rockchip,rk3568-i2s-tdm@ D4%=A5FqFq?C9mclk_txmclk_rxhclkbftxPQ xtx-mrx-ma M disabled i2s@fe410000,rockchip,rk3568-i2s-tdmA D5%EI5FqFqGK:mclk_txmclk_rxhclkbbfrxtxRS xtx-mrx-ma default0cdefghijklmnM disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB D6%M5FqOO;mclk_txmclk_rxhclkbbftxrxTxtx-ma defaultopqrM disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC D7SW<mclk_txmclk_rxhclkbbftxrxUV xtx-mrx-ma M disabledpdm@fe440000,rockchip,rk3568-pdmD DLZYpdm_clkpdm_hclkb frxstuvwxdefaultXxpdm-mM disabledspdif@fe460000,rockchip,rk3568-spdifF Df mclkhclk_\bftxdefaultyM disableddma-controller@fe530000,arm,pl330arm,primecellS@D p  apb_pclk&dma-controller@fe550000,arm,pl330arm,primecellU@Dp  apb_pclkbi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ D/HG i2cpclkzdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ D0JI i2cpclk{default  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ D1LK i2cpclk|default  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] D2NM i2cpclk}default  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ D3PO i2cpclk~default  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` D tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia DgRQspiclkapb_pclk&&ftxrxdefault   disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib DhTSspiclkapb_pclk&&ftxrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic DiVUspiclkapb_pclk&&ftxrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid DjXWspiclkapb_pclk&&ftxrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Dubaudclkapb_pclk&&default  disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Dv# baudclkapb_pclk&&default okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Dw'$baudclkapb_pclk&&default  disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Dx+(baudclkapb_pclk&& default  disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Dy/,baudclkapb_pclk& & default  disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Dz30baudclkapb_pclk& & default  disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk D{74baudclkapb_pclk&&default  disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl D|;8baudclkapb_pclk&&default  disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm D}?<baudclkapb_pclk&&default  disabledthermal-zonescpu-thermaldtripscpu_alert0ppassivecpu_alert1$passivecpu_crits criticalcooling-mapsmap00 gpu-thermaltripsgpu-thresholdppassivegpu-target$passivegpu-crits criticalcooling-mapsmap0 tsadc@fe710000,rockchip,rk3568-tsadcq Ds%5f@ `tsadcapb_pclka sdefaultsleep  okay ( ?saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr D]saradcapb_pclk xsaradc-apb Zokay lpwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault" disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault" disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault" disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault" disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault" disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault" disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault" disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault" disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault"okaypwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault" disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault" disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault" disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe%"5xphy x  okay phy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe%%5xphy x  okayphy@fe870000,rockchip,rk3568-csi-dphyypclk xapba  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz  xapb disabledNmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{  xapb disabledOusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m D okayhost-port  disabledotg-port okay usb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m D okayhost-port okay otg-port okay pinctrl,rockchip,rk3568-pinctrla ^S bgpio@fdd60000,rockchip,gpio-bank D!.    5J#gpio@fe740000,rockchip,gpio-bankt D"cd   5JWgpio@fe750000,rockchip,gpio-banku D#ef  @  5Jgpio@fe760000,rockchip,gpio-bankv D$gh  `  5Jgpio@fe770000,rockchip,gpio-bankw D%ij   5Jpcfg-pull-up pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camcan0can0m0-pins ,  can1can1m0-pins ,can2can2m0-pins ,  cifclk32kclk32k-out0 ,cpuebcedpdpemmcemmc-bus8 ,  ^emmc-clk ,_emmc-cmd ,`emmc-datastrobe ,aeth0eth1flashfspifspi-pins` ,]gmac0gmac1gpuhdmitxhdmitxm0-cec ,Rhdmitx-scl ,Phdmitx-sda ,Qi2c0i2c0-xfer ,  !i2c1i2c1-xfer ,  zi2c2i2c2m0-xfer , {i2c3i2c3m0-xfer ,|i2c4i2c4m0-xfer ,  }i2c5i2c5m0-xfer ,  ~i2s1i2s1m0-lrckrx ,fi2s1m0-lrcktx ,ei2s1m0-sclkrx ,di2s1m0-sclktx ,ci2s1m0-sdi0 , gi2s1m0-sdi1 , hi2s1m0-sdi2 , ii2s1m0-sdi3 ,ji2s1m0-sdo0 ,ki2s1m0-sdo1 ,li2s1m0-sdo2 , mi2s1m0-sdo3 , ni2s2i2s2m0-lrcktx ,pi2s2m0-sclktx ,oi2s2m0-sdi ,qi2s2m0-sdo ,ri2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk ,spdmm0-clk1 ,tpdmm0-sdi0 , updmm0-sdi1 , vpdmm0-sdi2 , wpdmm0-sdi3 ,xpmicpmic_int ,$pmupwm0pwm0m0-pins ,(pwm1pwm1m0-pins ,)pwm2pwm2m0-pins ,*pwm3pwm3-pins ,+pwm4pwm4-pins ,pwm5pwm5-pins ,pwm6pwm6-pins ,pwm7pwm7-pins ,pwm8pwm8m0-pins , pwm9pwm9m0-pins , pwm10pwm10m0-pins , pwm11pwm11m0-pins ,pwm12pwm12m1-pins ,pwm13pwm13m0-pins ,pwm14pwm14m0-pins ,pwm15pwm15m0-pins ,refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ,Ysdmmc0-clk ,Zsdmmc0-cmd ,[sdmmc1sdmmc2spdifspdifm0-tx ,yspi0spi0m0-pins0 , spi0m0-cs0 ,spi0m0-cs1 ,spi1spi1m0-pins0 , spi1m0-cs0 ,spi1m0-cs1 ,spi2spi2m0-pins0 ,spi2m0-cs0 ,spi2m0-cs1 ,spi3spi3m0-pins0 ,  spi3m0-cs0 ,spi3m0-cs1 ,tsadctsadc-shutorg ,tsadc-pin ,uart0uart0-xfer ,'uart1uart1m0-xfer ,  uart2uart2m0-xfer ,uart3uart3m0-xfer ,uart4uart4m0-xfer ,uart5uart5m0-xfer ,uart6uart6m0-xfer ,uart7uart7m0-xfer ,uart8uart8m0-xfer ,uart9uart9m0-xfer ,vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsled_user_en ,pciepcie20-reset-h , Vpcie30x1-enable-h ,pcie30x1-reset-h ,pcie30x2-reset-h ,pcie-enable-h ,usbminipcie-enable-h ,ngffpcie-enable-h ,vbus_typec_en ,opp-table-0,operating-points-v2 :opp-408000000 EQ L P P0 Z@opp-600000000 E#F L P P0 Z@opp-816000000 E0, L P P0 Z@ kopp-1104000000 EAʹ L 0 Z@opp-1416000000 ETfr L0 Z@opp-1608000000 E_" L0 Z@opp-1800000000 EkI L000 Z@opp-1992000000 Ev L000 Z@opp-table-1,operating-points-v2Fopp-200000000 E  L P PB@opp-300000000 E L P PB@opp-400000000 Eׄ L P PB@opp-600000000 E#F L B@opp-700000000 E)' L~~B@opp-800000000 E/ LB@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob D^ sata-phy disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon ?qos@fe190100,rockchip,rk3568-qossyscon @qos@fe190200,rockchip,rk3568-qossyscon Asyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy &'wrefclk_mrefclk_npclkxphy wokay pcie@fe270000,rockchip,rk3568-pcie k($aclk_mstaclk_slvaclk_dbipclkauxpci<DHsyspmcmsglegacyerrJu`U pcie-phy0@@'Tb @@@Cdbiapbconfigxpipeokaydefault #legacy-interrupt-controller5J Dpcie@fe280000,rockchip,rk3568-pcie k /($aclk_mstaclk_slvaclk_dbipclkauxpci<DHsyspmcmsglegacyerrJu` U  pcie-phy0@(Tb @@Cdbiapbconfigxpipeokaydefault Xlegacy-interrupt-controller5J Dethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*DHmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref xstmmacetha  disabledmdio,snps,dwmac-mdio stmmac-axi-configrx-queues-configqueue0tx-queues-config-queue0can@fe570000,rockchip,rk3568v2-canfdW DA@ baudpclkUT xcoreapbdefault disabledcan@fe580000,rockchip,rk3568v2-canfdX DCB baudpclkWV xcoreapbdefault disabledcan@fe590000,rockchip,rk3568v2-canfdY DED baudpclkYX xcoreapbdefault disabledphy@fe820000,rockchip,rk3568-naneng-combphy| refapbpipe%5xphy x  okaychosen serial2:115200n8gpio-leds ,gpio-ledsled-0 # heartbeat  heartbeatdefaultregulator-pcie30-avdd0v9,regulator-fixedpcie30_avdd0v9  %regulator-pcie30-avdd1v8,regulator-fixedpcie30_avdd1v8w@w@%regulator-vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z"%regulator-vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@"regulator-vcc5v-input,regulator-fixed vcc5v_inputLK@LK@"pwm-leds,pwm-leds-multicolormulti-led  status led-red  B@led-green  B@led-blue  B@regulator-vbus-typec,regulator-fixed  #default vbus_typecLK@LK@regulator-vcc3v3-minipcie,regulator-fixed  defaultvcc3v3_minipcie2Z2ZXregulator-vcc3v3-ngff,regulator-fixed  #default vcc3v3_ngff2Z2Zregulator-vcc3v3-pcie30x1,regulator-fixed  #defaultvcc3v3_pcie30x12Z2Zregulator-vcc3v3-pi6c-05,regulator-fixed  #default vcc3v3_pcie2Z2ZX interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsstatusarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsphy-supplyrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfdata-lanesstdout-pathfunctioncolorlinux,default-triggermax-brightnesspwmsenable-active-highgpio