8 (  !,ARM Corstone1000 FPGA MPS3 board2arm,corstone1000-mps3aliases=/soc/serial@1a510000E/soc/serial@1a520000chosenMserial0:115200n8cpus cpu@0Ycpu2arm,cortex-a35eimemory@88200000Ymemorye winterrupt-controller@1c000000 2arm,gic-400z e    l2-cache02cache@clock-100000000 2fixed-clock apb_pclkclock-48000000 2fixed-clocklsmclktimer2arm,armv8-timer0   clock-50000000 2fixed-clockuartclkpsci2arm,psci-1.0arm,psci-0.2#smcsoc 2simple-bus *timer@1a2200002arm,armv7-timer-meme" *frame@1a2300001 e#serial@1a5100002arm,pl011arm,primecelleQ >Euartclkapb_pclkserial@1a5200002arm,pl011arm,primecelleR >Euartclkapb_pclkmailbox@1b8200002arm,mhuv2-txarm,primecelle> Eapb_pclk -Q]qokay xdisabledmailbox@1b8300002arm,mhuv2-rxarm,primecelle> Eapb_pclk .Q]qokay xdisabledethernet@40100002smsc,lan9220smsc,lan9115e@mii tusb@402000002nxp,usb-isp1763e@  rhost interrupt-parent#address-cells#size-cellsmodelcompatibleserial0serial1stdout-pathdevice_typeregnext-level-cache#interrupt-cellsinterrupt-controllerinterruptsphandlecache-unifiedcache-levelcache-sizecache-line-sizecache-sets#clock-cellsclock-frequencyclock-output-namesmethodrangesframe-numberclocksclock-names#mbox-cellsarm,mhuv2-protocolssecure-statusphy-modereg-io-widthsmsc,irq-push-pullbus-widthdr_mode