8(|$mediatek,mt8183-evbmediatek,mt8183 +!7MediaTek MT8183 evaluation board =embeddedaliasesJ/soc/i2c@11007000O/soc/i2c@11011000T/soc/i2c@11009000Y/soc/i2c@1100f000^/soc/i2c@11008000c/soc/i2c@11016000h/soc/i2c@11005000m/soc/i2c@1101a000r/soc/i2c@1101b000w/soc/i2c@11014000|/soc/i2c@11015000/soc/i2c@11017000/soc/ovl@14008000/soc/ovl@14009000/soc/ovl@1400a000/soc/rdma@1400b000/soc/rdma@1400c000/soc/serial@11002000opp-table-cluster0operating-points-v2 opp0-793000000/D8@ opp0-9100000006= }opp0-1014000000opp0-1417000000Tu@ Popp0-1508000000YA A opp0-1586000000^p 6 opp0-1625000000`ۈ@  opp0-1677000000c@5 opp0-1716000000fHf opp0-1781000000j'@opp0-1846000000nB@opp0-1924000000ropp0-1989000000v@opp-table-cluster1operating-points-v2$opp1-793000000/D8@ `opp1-9100000006= opp1-1014000000opp-689000000)N@ Popp-767000000-} A opp-8450000002]@ 6 opp-8710000003g  opp-92300000075 opp-9620000009Vf opp-1027000000=6opp-1092000000AB@opp-1144000000D0opp-1196000000GIccimediatek,mt8183-ccicciintermediate"cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3cpu@0cpuarm,cortex-a53*.psci<Ocpuintermediate _Ty@@!"cpu@1cpuarm,cortex-a53*.psci<Ocpuintermediate _Ty@@!"cpu@2cpuarm,cortex-a53*.psci<Ocpuintermediate _Ty@@!"cpu@3cpuarm,cortex-a53*.psci<Ocpuintermediate _Ty@@!"cpu@100cpuarm,cortex-a73*.psci<O#cpuintermediate$_y@@%"&cpu@101cpuarm,cortex-a73*.psci<O#cpuintermediate$_y@@%"&cpu@102cpuarm,cortex-a73*.psci<O#cpuintermediate$_y@@%"&cpu@103cpuarm,cortex-a73*.psci<O#cpuintermediate$_y@@%"&idle-statespscicpu-sleeparm,idle-state 3DT cluster-sleep-0arm,idle-state 3DTcluster-sleep-1arm,idle-state 3DT#l2-cache0cachee{@q!l2-cache1cachee{@q%opp-table-0operating-points-v2^opp-300000000 hopp-320000000 opp-340000000C <opp-360000000u* Ҧopp-380000000W opp-400000000ׄ zopp-420000000 opp-460000000k  Lopp-500000000e }opp-540000000 / `opp-580000000" 4opp-620000000$s opp-653000000&@ YFopp-698000000) opp-743000000,IG opp-800000000/ pmu-a53arm,cortex-a53-pmu '(pmu-a73arm,cortex-a73-pmu ')psci arm,psci-1.05smcfixed-factor-clock-13mfixed-factor-clock*clk13m5oscillator fixed-clockclk26m*timerarm,armv8-timer '@   soc+ simple-busefuse@8000000%mediatek,mt8183-efusemediatek,efuse*+ disabledinterrupt-controller@c000000 arm,gic-v3 'P*   @ A B  'ppi-partitionsinterrupt-partition-0(interrupt-partition-1)syscon@c530000mediatek,mt8183-mcucfgsyscon* Sinterrupt-controller@c530a80.mediatek,mt8183-sysirqmediatek,mt6577-sysirq '* S Pcpu-debug@d410000&arm,coresight-cpu-debugarm,primecell* A+. apb_pclkcpu-debug@d510000&arm,coresight-cpu-debugarm,primecell* Q+. apb_pclkcpu-debug@d610000&arm,coresight-cpu-debugarm,primecell* a+. apb_pclkcpu-debug@d710000&arm,coresight-cpu-debugarm,primecell* q+. apb_pclkcpu-debug@d810000&arm,coresight-cpu-debugarm,primecell* +. apb_pclkcpu-debug@d910000&arm,coresight-cpu-debugarm,primecell* +. apb_pclkcpu-debug@da10000&arm,coresight-cpu-debugarm,primecell* +. apb_pclkcpu-debug@db10000&arm,coresight-cpu-debugarm,primecell* +. apb_pclksyscon@10000000 mediatek,mt8183-topckgensyscon*syscon@10001000 mediatek,mt8183-infracfgsyscon* +syscon@10003000mediatek,mt8183-pericfgsyscon*0Qpinctrl@10005000mediatek,mt8183-pinctrl*PDiocfg0iocfg1iocfg2iocfg3iocfg4iocfg5iocfg6iocfg7iocfg8eint#3?, ,i2c0=pins_i2cKRSRi2c1Ipins_i2cKQTRi2c2?pins_i2cKghRi2c3Gpins_i2cK23Ri2c4>pins_i2cKijRi2c5Lpins_i2cK01Rspi0@pins_spiKUVWXgmmc0defaultTpins_cmd_dat$K{}~ztpins_clkK|pins_rstKmmc0Upins_cmd_dat$K{}~zt epins_clkK| fpins_dsK fpins_rstK mmc1defaultXpins_cmd_datK "!tpins_clkKtpins_pmuKmmc1Ypins_cmd_datK "!tepins_clkKftspi1Hpins_spiKgspi2Jpins_spiK^gspi3Kpins_spiKgspi4Mpins_spiKgspi5Npins_spiK gpwm1Fpins_pwmKZsyscon@10006000)mediatek,mt8183-scpsyssysconsimple-mfd*`power-controller!mediatek,mt8183-power-controller+Epower-domain@0* +/+7audioaudio1audio2power-domain@1*+power-domain@2*mfg+power-domain@3*+-power-domain@4*power-domain@5*power-domain@6*+power-domain@7*X.......... 5mmmm-0mm-1mm-2mm-3mm-4mm-5mm-6mm-7mm-8mm-9+/+power-domain@8*@00 00000.camcam-0cam-1cam-2cam-3cam-4cam-5cam-6+/power-domain@9* "1 1ispisp-0isp-1+/power-domain@10* /power-domain@11* /power-domain@12* @&#222222-vpuvpu1vpu-0vpu-1vpu-2vpu-3vpu-4vpu-5+/+power-domain@13* $vpu2+power-domain@14*%vpu3+watchdog@10007000mediatek,mt8183-wdt*p Rsyscon@1000c000"mediatek,mt8183-apmixedsyssyscon*Bpwrap@1000d000mediatek,mt8183-pwrap*pwrap )+ spiwrappmicmediatek,mt6358 ,mt6358codecmediatek,mt6358-sound mt6358regulatormediatek,mt6358-regulatorbuck_vdram1 vdram1/ GL_0tbuck_vcore vcore/ G_jtbuck_vpa vpa/ G7_Ptbuck_vproc11 vproc11/ G_jt&buck_vproc12 vproc12/ G_jtbuck_vgpu vgpu/ hG _jt3-buck_vs2 vs2/ GL_0tbuck_vmodem vmodem/ G_jtbuck_vs1 vs1/B@G'{l_0tldo_vdram2 vdram2/ 'Gw@t ldo_vsim1 vsim1/G/M`tldo_vibr vibr/OG2Zt<ldo_vrf12 vrf12/OGOtxldo_vio18 vio18/w@Gw@t Wldo_vusb vusb/-G/M`tldo_vcamio vcamio/w@Gw@tEldo_vcamd vcamd/ Gw@tEldo_vcn18 vcn18/w@Gw@tldo_vfe28 vfe28/*G*tldo_vsram_proc11  vsram_proc11/ G_jtldo_vcn28 vcn28/*G*tldo_vsram_others  vsram_others/ G_jtldo_vsram_gpu  vsram_gpu/ PGB@_jt-3ldo_vxo22 vxo22/!G!txldo_vefuse vefuse/Gtldo_vaux18 vaux18/w@Gw@tldo_vmch vmch/,@ G2Zt<Zldo_vbif28 vbif28/*G*tldo_vsram_proc12  vsram_proc12/ G_jtldo_vcama1 vcama1/w@G-tEldo_vemc vemc/,@ G2Zt<Vldo_vio28 vio28/*G*tldo_va12 va12/OGOtldo_vrf18 vrf18/w@Gw@txldo_vcn33 vcn33/2ZG5gtldo_vcama2 vcama2/w@G-tEldo_vmc vmc/w@G2Zt<[ldo_vldo28 vldo28/*G-tldo_vaud28 vaud28/*G*tldo_vsim2 vsim2/G/M`trtcmediatek,mt6358-rtckeysmediatek,mt6358-keyspowerthomefkeyboard@10010000mediatek,mt6779-keypad* *kpd disabledscp@10500000mediatek,mt8183-scp *P\ sramcfg +main 4 disabledbtimer@10017000,mediatek,mt8183-timermediatek,mt6765-timer*p 5iommu@10205000mediatek,mt8183-m4u* P 6789:;<*`mailbox@10238000mediatek,mt8183-gce*#@ 7+gce_auxadc@11001000.mediatek,mt8183-auxadcmediatek,mt8173-auxadc*+#mainCokayAserial@11002000*mediatek,mt8183-uartmediatek,mt6577-uart*  [ *+ baudbusokayserial@11003000*mediatek,mt8183-uartmediatek,mt6577-uart*0 \ *+ baudbus disabledserial@11004000*mediatek,mt8183-uartmediatek,mt6577-uart*@ ] *+ baudbus disabledi2c@11005000mediatek,mt8183-i2c *P W+W+* maindma+ disabledi2c@11007000mediatek,mt8183-i2c *p Q+ +* maindma+okayUdefaultc=i2c@11008000mediatek,mt8183-i2c * R+ +*+G maindmaarb+okayUdefaultc>B@i2c@11009000mediatek,mt8183-i2c * S+ +*+I maindmaarb+okayUdefaultc?spi@1100a000mediatek,mt8183-spi+* x6+parent-clksel-clkspi-clkokayUdefaultc@mthermal-sensor@1100b000mediatek,mt8183-thermal* + +# thermauxadc+ LABCcalibration-dataesvs@1100bc00mediatek,mt8183-svs* + mainDC(svs-calibration-datat-calibration-datapwm@1100e000mediatek,mt8183-disp-pwm* E+5mainmmpwm@11006000mediatek,mt8183-pwm*`0++++++topmainpwm1pwm2pwm3pwm4okaycFUdefaulti2c@1100f000mediatek,mt8183-i2c * T+ +* maindma+okayUdefaultcGspi@11010000mediatek,mt8183-spi+* |6+8parent-clksel-clkspi-clkokayUdefaultcHmi2c@11011000mediatek,mt8183-i2c * U+9+* maindma+okayUdefaultcIspi@11012000mediatek,mt8183-spi+*  6+;parent-clksel-clkspi-clkokayUdefaultcJmspi@11013000mediatek,mt8183-spi+*0 6+<parent-clksel-clkspi-clkokayUdefaultcKmi2c@11014000mediatek,mt8183-i2c *@ +H+*+G maindmaarb+ disabledi2c@11015000mediatek,mt8183-i2c *P +J+*+I maindmaarb+ disabledi2c@11016000mediatek,mt8183-i2c *` V+D+*+E maindmaarb+okayUdefaultcLB@i2c@11017000mediatek,mt8183-i2c *p +F+*+E maindmaarb+ disabledspi@11018000mediatek,mt8183-spi+* 6+Kparent-clksel-clkspi-clkokayUdefaultcMmspi@11019000mediatek,mt8183-spi+* 6+Lparent-clksel-clkspi-clkokayUdefaultcNmi2c@1101a000mediatek,mt8183-i2c * X+b+* maindma+ disabledi2c@1101b000mediatek,mt8183-i2c * Y+c+* maindma+ disabledusb@11201000#mediatek,mt8183-mtu3mediatek,mtu3 * . > macippc HOP+=+Zsys_ckref_ck Q e+ disabledusb@11200000'mediatek,mt8183-xhcimediatek,mtk-xhci* mac I+=+Zsys_ckref_ck disabledaudio-controller@11220000 mediatek,mt8183-audiosyssyscon*"Smt8183-afe-pcmmediatek,mt8183-audio R audiosysEDSSSSS SSSSS S S S SS+/+7  0HLKOtuvwxyz{|}~*waud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adc_adda6_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_i2s1_bclk_swaud_i2s2_bclk_swaud_i2s3_bclk_swaud_i2s4_bclk_swaud_tdm_clkaud_tml_clkaud_infra_clkmtkaif_26m_clktop_mux_audiotop_mux_aud_intbustop_syspll_d2_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d8top_mux_aud_eng2top_apll2_d8top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_clk26m_clkmmc@11230000mediatek,mt8183-mmc *# M++sourcehclksource_cgokayUdefaultstate_uhscT U*4 BTcr(VWUmmc@11240000mediatek,mt8183-mmc *$ N ++(sourcehclksource_cgokayUdefaultstate_uhscX Y*4  'Z[.dsi-phy@11e50000mediatek,mt8183-mipi-tx*BD mipi_tx0_pll\calibration-dataaefuse@11f10000%mediatek,mt8183-efusemediatek,efuse*+socinfo-data1@4c*Lsocinfo-data2@60*`calib@180* Ccalib@190* \calib@580*dDt-phy@11f40000.mediatek,mt8183-tphymediatek,generic-tphy-v2+okayusb-phy@0**refDOokayOusb-phy@700* *refDokayPsyscon@13000000mediatek,mt8183-mfgcfgsyscon*E]gpu@13040000'mediatek,mt8183b-maliarm,mali-bifrost*@$ _jobmmugpu]EEEocore0core1core2^-syscon@14000000mediatek,mt8183-mmsyssyscon* ___.dma-controller0@14001000mediatek,mt8183-mdp3-rdma*_E. .` __mdp3-rsz0@14003000mediatek,mt8183-mdp3-rsz*0_0.mdp3-rsz1@14004000mediatek,mt8183-mdp3-rsz*@_@.dma-controller@14005000mediatek,mt8183-mdp3-wrot*P_P!E.`mdp3-wdma@14006000mediatek,mt8183-mdp3-wdma*`_`"E.)`ovl@14008000mediatek,mt8183-disp-ovl* E.`_ovl@14009000mediatek,mt8183-disp-ovl-2l* E.`_ovl@1400a000mediatek,mt8183-disp-ovl-2l* E.`_rdma@1400b000mediatek,mt8183-disp-rdma* E.`_rdma@1400c000mediatek,mt8183-disp-rdma* E.`_color@1400e0006mediatek,mt8183-disp-colormediatek,mt8173-disp-color* E._ccorr@1400f000mediatek,mt8183-disp-ccorr* E._aal@14010000mediatek,mt8183-disp-aal* E._gamma@14011000mediatek,mt8183-disp-gamma* E._dither@14012000mediatek,mt8183-disp-dither*  E._ dsi@14014000mediatek,mt8183-dsi*@ E.. aenginedigitalhs.adphymutex@14016000mediatek,mt8183-disp-mutex*` E_`larb@14017000mediatek,mt8183-smi-larb*p/..Eapbsmi6smi@14019000mediatek,mt8183-smi-common* ....apbsmigals0gals1E/mdp3-ccorr@1401c000mediatek,mt8183-mdp3-ccorr*_1.+syscon@15020000mediatek,mt8183-imgsyssyscon*1larb@15021000mediatek,mt8183-smi-larb*/1 1 . apbsmigalsE ;larb@1502f000mediatek,mt8183-smi-larb*/11.  apbsmigalsE 8syscon@16000000mediatek,mt8183-vdecsyssyscon*cvideo-codec@16020000mediatek,mt8183-vcodec-dec* 0@Phpx(miscldtopcmadavpphwdhwqhwbhwg 8` `!`"`#`$`%`&bcE cvdeclarb@16010000mediatek,mt8183-smi-larb*/ccapbsmiE 7syscon@17000000mediatek,mt8183-vencsyssyscon*dlarb@17010000mediatek,mt8183-smi-larb*/ddapbsmiE :jpeg-encoder@17030000+mediatek,mt8183-jpgencmediatek,mtk-jpgenc* ``E djpgencsyscon@19000000 mediatek,mt8183-ipu_connsyscon*2syscon@19010000mediatek,mt8183-ipu_adlsyscon*syscon@19180000!mediatek,mt8183-ipu_core0syscon*syscon@19280000!mediatek,mt8183-ipu_core1syscon*(syscon@1a000000mediatek,mt8183-camsyssyscon*0larb@1a001000mediatek,mt8183-smi-larb*/00. apbsmigalsE<larb@1a002000mediatek,mt8183-smi-larb* /0 0 . apbsmigalsE9thermal-zonescpu-thermald)7eGtripstrip-point0Y eEpassivetrip-point1Y8eEpassivefcpu-critY8e Ecriticalcooling-mapsmap0pf0u map1pf0usoc-thermal)7eGtripstrip-alertYLeEpassivetrip-critYe Ecriticalgpu-thermal)7eGtripstrip-alertYLeEpassivetrip-critYe Ecriticalmd1-thermal)7eGtripstrip-alertYLeEpassivetrip-critYe Ecriticalcpu-little-thermal)7eGtripstrip-alertYLeEpassivetrip-critYe Ecriticalcpu-big-thermal)7eGtripstrip-alertYLeEpassivetrip-critYe Ecriticaltsabb-thermal)7eGtripstrip-alertYLeEpassivetrip-critYe Ecriticalmemory@40000000memory*@chosenserial0:921600n8reserved-memory+memory@50000000shared-dma-pool*P4thermal-sensormurata,ncp03wf104w@pA compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11ovl0ovl-2l0ovl-2l1rdma0rdma1serial0opp-sharedphandleopp-hzopp-microvoltrequired-oppsclocksclock-namesoperating-points-v2proc-supplycpudevice_typeregenable-methodcapacity-dmips-mhzcpu-idle-statesdynamic-power-coefficienti-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsmediatek,ccientry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterrupts#clock-cellsclock-divclock-multclock-output-namesclock-frequencyrangesstatus#interrupt-cellsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxmediatek,pull-up-advbias-disableinput-enablebias-pull-upbias-pull-downdrive-strengthoutput-high#power-domain-cellsmediatek,infracfgdomain-supplymediatek,smiinterrupts-extendedmediatek,dmic-moderegulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-enable-ramp-delayregulator-always-onregulator-allowed-modesregulator-coupled-withregulator-coupled-max-spreadlinux,keycodeswakeup-sourcememory-regionmediatek,larbs#iommu-cells#mbox-cells#io-channel-cellspinctrl-namespinctrl-0mediatek,pad-select#thermal-sensor-cellsresetsmediatek,auxadcmediatek,apmixedsysnvmem-cellsnvmem-cell-namespower-domains#pwm-cellsphysmediatek,syscon-wakeupreset-namespinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplyassigned-clocksassigned-clock-parentsnon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104cap-sdio-irqno-mmckeep-power-in-suspend#phy-cellsmediatek,discthinterrupt-namespower-domain-namesmali-supplymboxesmediatek,gce-client-regmediatek,gce-eventsiommus#dma-cellsmediatek,rdma-fifo-sizephy-namesmediatek,scpmediatek,vdecsyspolling-delay-passivepolling-delaythermal-sensorssustainable-powertemperaturehysteresistripcooling-devicecontributionstdout-pathno-mappullup-uvpullup-ohmpulldown-ohmio-channels