&8}@(}$mediatek,mt8188-evbmediatek,mt8188 +!7MediaTek MT8188 evaluation boardcpus+cpu@0=cpuarm,cortex-a55IMpsci[w5k~@@cpu@100=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@200=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@300=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@400=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@500=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@600=cpuarm,cortex-a78IMpsci[k~@@cpu@700=cpuarm,cortex-a78IMpsci[k~@@cpu-mapcluster0core0core1 core2 core3 core4 core5 core6core7idle-statespscicpu-off-larm,idle-state6G2X_hDcpu-off-barm,idle-state6G-Xhcluster-off-larm,idle-state6G7XhHcluster-off-barm,idle-state6G2Xhl2-cache0cachey@l2-cache1cachey@l3-cachecachey @oscillator-13m fixed-clock[]@clk13m%oscillator-26m fixed-clock[clk26m'oscillator-32k fixed-clock[clk32kopp-table-gpuoperating-points-v2Bopp-390000000>opp-431000000opp-4730000001h@ 'opp-515000000F Xopp-556000000!# hopp-598000000# <opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-8350000001 (ropp-8800000004s qopp-9150000006 Xopp-915000000-56 0opp-915000000-66 qpopp-9500000008ـ 5opp-950000000-58ـ X0opp-950000000-68ـ qppmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Tsmctimerarm,armv8-timer @   []@soc+ simple-businterrupt-controller@c000000 arm,gic-v3  I    ppi-partitionsinterrupt-partition-03 interrupt-partition-13syscon@10000000 mediatek,mt8188-topckgensysconIsyscon@10001000#mediatek,mt8188-infracfg-aosysconIsyscon@10003000mediatek,mt8188-pericfgsysconI0.pinctrl@10005000mediatek,mt8188-pinctrl`IP0=ui2c4-pins<pins-busn@?ui2c5-pins?pins-busnBAui2c6-pins@pins-busnDCummc0-default-pins1pins-cmd-dat$nuepins-clknfpins-rstnuemmc0-uhs-pins2pins-cmd-dat$nuepins-clk-dsnfpins-rstnuenor-pins9pins-io-ck n}pins-io-cs n~uspi0-pins)pins-spinEFGHspi1-pins*pins-spinKLMNspi2-pins+pins-spinOPQRuart0-pins(pins-rx-txn usyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfdI`power-controller!mediatek,mt8188-power-controller+Cpower-domain@0I+power-domain@1Imfgalt+power-domain@2Ipower-domain@3Ipower-domain@4Ipower-domain@15I 34=   topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1+power-domain@16IHAcfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-bus+power-domain@20I08cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6power-domain@23Iss-vdecpower-domain@22Iss-vdecpower-domain@29I  camccubuscfgck+power-domain@30I(6ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsys+power-domain@32I $ss-camb-subss-camb-rawss-camb-yuvpower-domain@31I$ss-cama-subss-cama-rawss-cama-yuvpower-domain@17I(  &cfgckcfgxoss-larb2ss-larb3ss-gals+power-domain@9I @? bushdcppower-domain@18Ipower-domain@19Ipower-domain@24I !!!!0ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-srampower-domain@21I""ss-wpe-l7ss-wpe-l7pcepower-domain@5I# ss-pextp-fmempower-domain@7I01seninf0seninf1power-domain@6Ipower-domain@10I ED busmain+power-domain@11I +power-domain@14IFasmpower-domain@13I S$a1sysintbusadspckpower-domain@12I power-domain@8I#  ethermacwatchdog@10007000mediatek,mt8188-wdtIp syscon@1000c000"mediatek,mt8188-apmixedsyssysconI=timer@10017000,mediatek,mt8188-timermediatek,mt6765-timerIp %pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsysconI@   7 maindma+okaydefault?[i2c@11ec1000mediatek,mt8188-i2c I">7 maindma+okaydefault@[clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-enI >gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jmI@A0~} ?jobmmugpuOBcCCCqcore0core1core2 disabledclock-controller@13fbf000mediatek,mt8188-mfgcfgIAclock-controller@14000000mediatek,mt8188-vppsys0Iclock-controller@14e00000mediatek,mt8188-wpesysI"clock-controller@14e02000mediatek,mt8188-wpesys-vpp0I clock-controller@14f00000mediatek,mt8188-vppsys1Iclock-controller@15000000mediatek,mt8188-imgsysIclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topIclock-controller@15130000mediatek,mt8188-imgsys1-dip-nrIclock-controller@15220000mediatek,mt8188-imgsys-wpe1I"clock-controller@15330000mediatek,mt8188-ipesysI3clock-controller@15520000mediatek,mt8188-imgsys-wpe2IRclock-controller@15620000mediatek,mt8188-imgsys-wpe3Ibclock-controller@16000000mediatek,mt8188-camsysIclock-controller@1604f000mediatek,mt8188-camsys-rawaIclock-controller@1606f000mediatek,mt8188-camsys-yuvaIclock-controller@1608f000mediatek,mt8188-camsys-rawbIclock-controller@160af000mediatek,mt8188-camsys-yuvbI clock-controller@17200000mediatek,mt8188-ccusysI clock-controller@1800f000mediatek,mt8188-vdecsys-socIclock-controller@1802f000mediatek,mt8188-vdecsysIclock-controller@1a000000mediatek,mt8188-vencsysI!syscon@1c01d000mediatek,mt8188-vdosys0sysconI DDsyscon@1c100000mediatek,mt8188-vdosys1sysconI  DD aliases/soc/serial@11001100/soc/i2c@11280000/soc/i2c@11e00000/soc/i2c@11281000/soc/i2c@11282000/soc/i2c@11e01000/soc/i2c@11ec0000/soc/i2c@11ec1000/soc/mmc@11230000chosenserial0:115200n8memory@40000000=memoryI@reserved-memory+memory@50000000shared-dma-poolIP& compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinityreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upinput-enabledrive-strengthbias-pull-downbias-disable#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrst#reset-cellsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsmemory-regionstatuspinctrl-namespinctrl-0#io-channel-cellsphysassigned-clocksassigned-clock-parentsmediatek,syscon-wakeupwakeup-sourcebus-widthhs400-ds-delaymax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdnon-removablevmmc-supplyvqmmc-supplypinctrl-1clock-divspi-max-frequency#phy-cellsinterrupt-namesoperating-points-v2power-domainspower-domain-namesmboxesmediatek,gce-client-regserial0i2c0i2c1i2c2i2c3i2c4i2c5i2c6mmc0stdout-pathno-map