8({X 3,Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2$2qcom,ipq5018-rdp432-c2qcom,ipq5018clockssleep-clk 2fixed-clock=J}Z xo-board-clk 2fixed-clock=Jn6Zcpus cpu@0bcpu2arm,cortex-a53nrpscicpu@1bcpu2arm,cortex-a53nrpscil2-cache2cacheZopp-table-cpu2operating-points-v2Zopp-800000000/ @opp-1008000000< @firmwarescm2qcom,scm-ipq5018qcom,scmmemory@40000000bmemoryn@pmu2arm,cortex-a53-pmu psci 2arm,psci-1.0ysmcreserved-memory bootloader@4a800000nJ %sbl@4aa00000nJ%smem@4ab00000 2qcom,smemnJ%,tz@4ac00000nJ %soc@0 2simple-bus phy@5b0002qcom,ipq5018-usb-hsphyn w4O;FokayZ pinctrl@10000002qcom,ipq5018-tlmmn0 M]i/uZuart1-stategpio31gpio32gpio33gpio34 blsp1_uart1Z sdc-default-stateZ clk-pinsgpio9 sdc1_clkcmd-pinsgpio8 sdc1_cmddata-pinsgpio4gpio5gpio6gpio7 sdc1_dataclock-controller@18000002qcom,gcc-ipq5018n$ =Zhwlock@19050002qcom,tcsr-mutexnPZmmc@7804000%2qcom,ipq5018-sdhciqcom,sdhci-msm-v5n@hc{hc_irqpwr_irqYZifacecorexo"Fokay0 :defaultHUd qrdma-controller@78840002qcom,bam-v1.7.0n@ bam_clk|Z serial@78af000%2qcom,msm-uartdm-v1.4qcom,msm-uartdmn k coreifaceFokay0 :defaultspi@78b50002qcom,spi-qup-v2.2.1 nP _ coreiface  txrx Fdisabledusb@8af88002qcom,ipq5018-dwc3qcom,dwc3n > hs_phy_irq ufxvcoreifacesleepmock_utmi4b Fokayusb@8a00000 2snps,dwc3nvref  usb2-phy 7hostinterrupt-controller@b0000002qcom,msm-qgic2 n   @   u   Zv2m@02arm,gic-v2m-framen?v2m@10002arm,gic-v2m-framen?watchdog@b017000$2qcom,apss-wdt-ipq5018qcom,kpss-wdtn p@  mailbox@b111000<2qcom,ipq5018-apcs-apps-globalqcom,ipq6018-apcs-apps-globaln = pllxogpll0NZclock@b1160002qcom,ipq5018-a53plln `@=xoZtimer@b1200002arm,armv7-timer-memn  frame@b120000n   Zframe@b123000n 0  Z Fdisabledframe@b124000Z  n @ Fdisabledframe@b125000n P  Z Fdisabledframe@b126000n `  Z Fdisabledframe@b127000n p  Z Fdisabledframe@b128000n  Z Fdisabledtimer2arm,armv8-timer0aliasesg/soc@0/serial@78af000chosenoserial0:115200n8 interrupt-parent#address-cells#size-cellsmodelcompatible#clock-cellsclock-frequencyphandledevice_typeregenable-methodnext-level-cacheclocksoperating-points-v2cache-levelcache-sizecache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsqcom,sdi-enabledinterruptsrangesno-maphwlocksresets#phy-cellsstatusgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellspinsfunctiondrive-strengthbias-pull-downbias-disablebias-pull-up#reset-cells#hwlock-cellsreg-namesinterrupt-namesclock-namesnon-removablepinctrl-0pinctrl-namesmmc-ddr-1_8vmmc-hs200-1_8vmax-frequencybus-width#dma-cellsqcom,eedmasdma-namesqcom,select-utmi-as-pipe-clkphy-namesphystx-fifo-resizesnps,is-utmi-l1-suspendsnps,hird-thresholdsnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirkdr_modemsi-controller#mbox-cellsframe-numberserial0stdout-path