8((  ),Qualcomm Technologies, Inc. X1E80100 QCP 2qcom,x1e80100-qcpqcom,x1e80100chosen=serial0:115200n8clocksxo-board 2fixed-clockIYfsleep-clk 2fixed-clockI}Yf+bi-tcxo-div2-clk2fixed-factor-clockYnuf*bi-tcxo-ao-div2-clk2fixed-factor-clockYnufcpus cpu@0cpu 2qcom,oryonpscipscifl2-cache2cachefcpu@100cpu 2qcom,oryonpscipscifcpu@200cpu 2qcom,oryonpscipscifcpu@300cpu 2qcom,oryonpscipscifcpu@10000cpu 2qcom,oryonpsci  pscifl2-cache2cachef cpu@10100cpu 2qcom,oryonpsci  pscifcpu@10200cpu 2qcom,oryonpsci  pscifcpu@10300cpu 2qcom,oryonpsci  pscifcpu@20000cpu 2qcom,oryonpscipscifl2-cache2cachefcpu@20100cpu 2qcom,oryonpscipscifcpu@20200cpu 2qcom,oryonpscipscifcpu@20300cpu 2qcom,oryonpscipscifcpu-mapcluster0core0core1core2core3cluster1core0core1core2core3cluster2core0core1core2core3idle-statespscicpu-sleep-02arm,idle-stateret%<M@]fdomain-idle-statescluster-sleep-02domain-idle-statel2-ret%D<^M] f%cluster-sleep-12domain-idle-state ret-pll-off%T<M ]Xf&firmwarescm2qcom,scm-x1e80100qcom,scmn interconnect-02qcom,x1e80100-clk-virt|!f4interconnect-12qcom,x1e80100-mc-virt|!f memory@80000000memorypmu2arm,armv8-pmuv3 psci 2arm,psci-1.0smcpower-domain-cpu0"fpower-domain-cpu1"fpower-domain-cpu2"fpower-domain-cpu3"fpower-domain-cpu4#f power-domain-cpu5#f power-domain-cpu6#f power-domain-cpu7#f power-domain-cpu8$fpower-domain-cpu9$fpower-domain-cpu10$fpower-domain-cpu11$fpower-domain-cpu-cluster0%&'f"power-domain-cpu-cluster1%&'f#power-domain-cpu-cluster2%&'f$power-domain-systemf'reserved-memory gunyah-hyp@80000000hyp-elf-package@80800000 ncc@80a00000@cpucp-log@80e00000cpucp@80e40000Treserved-region@813800008tags-region@81400000@xbl-dtlog@81a00000xbl-ramdump@81a40000aop-image@81c00000aop-cmd-db@81c60000 2qcom,cmd-dbaop-config@81c80000tme-crash-dump@81ca0000tme-log@81ce0000@uefi-log@81ce4000@secdata-apss@81cff000pdp-ns-shared@81e00000gpu-prr@81f00000tpm-control@81f10000usb-ucsi-shared@81f20000pld-pep@81f30000`pld-gmu@81f36000`pld-pdp@81f37000ptz-stat@82700000pxbl-tmp-buffer@82800000adsp-rpc-remote-heap@84b00000spu-secure-shared-memory@853000000adsp-boot-dtb@866c0000lspss-region@86700000p@adsp-boot@86b00000video@87700000ppadspslpi@87e00000fq6-adsp-dtb@8b800000fcdsp@8b900000fq6-cdsp-dtb@8d900000fgpu-microcode@8d9fe000 fcvp@8da00000pcamera@8e100000av1-encoder@8e900000preserved-region@8f000000wpss@8fa00000q6-wpss-dtb@913000000xbl-sc@d8000000reserved-region@d8040000 qtee@d80e0000Rta@d8600000`tags@e1000000jllcc-lpi@ff800000`smem@ffe00000 2qcom,smem (linux,cma2shared-dma-poolsmp2p-adsp 2qcom,smp2p) )#-<master-kernelLmaster-kernel\fslave-kernel Lslave-kernelsfsmp2p-cdsp 2qcom,smp2p) )#^-<master-kernelLmaster-kernel\fslave-kernel Lslave-kernelsfsoc@0 2simple-bus clock-controller@1000002qcom,x1e80100-gcc 4n*+,-./01Yf3mailbox@4080002qcom,x1e80100-ipccqcom,ipcc@ sf)dma-controller@800000*2qcom,x1e80100-gpi-dmaqcom,sm6350-gpi-dma > 26 disabledf7geniqup@8c00002qcom,geni-se-qup n33 m-ahbs-ahb 2# okayi2c@8800002qcom,geni-i2c@ (n3seHn4456 qup-corequp-configqup-memory 77txrx"8,default  disabledspi@8800002qcom,geni-spi@ (n3seHn4456 qup-corequp-configqup-memory 77txrx"9:,default  disabledi2c@8840002qcom,geni-i2c@@ )n3seHn4456 qup-corequp-configqup-memory 77txrx";,default  disabledspi@8840002qcom,geni-spi@@ )n3seHn4456 qup-corequp-configqup-memory 77txrx"<=,default  disabledi2c@8880002qcom,geni-i2c@ *n3seHn4456 qup-corequp-configqup-memory 77txrx">,default  disabledspi@8880002qcom,geni-spi@ *n3seHn4456 qup-corequp-configqup-memory 77txrx"?@,default  disabledi2c@88c0002qcom,geni-i2c@ +n3seHn4456 qup-corequp-configqup-memory 77txrx"A,default  disabledspi@88c0002qcom,geni-spi@ +n3seHn4456 qup-corequp-configqup-memory 77txrx"BC,default  disabledi2c@8900002qcom,geni-i2c@ ,n3seHn4456 qup-corequp-configqup-memory 77txrx"D,default  disabledspi@8900002qcom,geni-spi@ ,n3seHn4456 qup-corequp-configqup-memory 77txrx"EF,default  disabledi2c@8940002qcom,geni-i2c@@ -n3seHn4456 qup-corequp-configqup-memory 77txrx"G,default  disabledspi@8940002qcom,geni-spi@@ -n3seHn4456 qup-corequp-configqup-memory 77txrx"HI,default  disabledserial@8940002qcom,geni-debug-uart@@ -n3se0n4456qup-corequp-config"J,defaultokayi2c@8980002qcom,geni-i2c@ n3seHn4456 qup-corequp-configqup-memory 77txrx"K,default  disabledspi@8980002qcom,geni-spi@ n3seHn4456 qup-corequp-configqup-memory 77txrx"LM,default  disabledi2c@89c0002qcom,geni-i2c@ n3seHn4456 qup-corequp-configqup-memory 77txrx"N,default  disabledspi@89c0002qcom,geni-spi@ n3seHn4456 qup-corequp-configqup-memory 77txrx"OP,default  disableddma-controller@a00000*2qcom,x1e80100-gpi-dmaqcom,sm6350-gpi-dma      > 26 disabledfRgeniqup@ac00002qcom,geni-se-qup n33 m-ahbs-ahb 2# okayi2c@a800002qcom,geni-i2c@  n3seHn4456Q qup-corequp-configqup-memory RRtxrx"S,default  disabledspi@a800002qcom,geni-spi@  n3seHn4456Q qup-corequp-configqup-memory RRtxrx"TU,default  disabledi2c@a840002qcom,geni-i2c@@ !n3seHn4456Q qup-corequp-configqup-memory RRtxrx"V,default  disabledspi@a840002qcom,geni-spi@@ !n3seHn4456Q qup-corequp-configqup-memory RRtxrx"WX,default  disabledi2c@a880002qcom,geni-i2c@ "n3seHn4456Q qup-corequp-configqup-memory RRtxrx"Y,default  disabledspi@a880002qcom,geni-spi@ "n3seHn4456Q qup-corequp-configqup-memory RRtxrx"Z[,default  disabledi2c@a8c0002qcom,geni-i2c@ #n3seHn4456Q qup-corequp-configqup-memory RRtxrx"\,default  disabledspi@a8c0002qcom,geni-spi@ #n3seHn4456Q qup-corequp-configqup-memory RRtxrx"]^,default  disabledi2c@a900002qcom,geni-i2c@ $n3seHn4456Q qup-corequp-configqup-memory RRtxrx"_,default  disabledspi@a900002qcom,geni-spi@ $n3seHn4456Q qup-corequp-configqup-memory RRtxrx"`a,default  disabledi2c@a940002qcom,geni-i2c@@ %n3seHn4456Q qup-corequp-configqup-memory RRtxrx"b,default  disabledspi@a940002qcom,geni-spi@@ %n3seHn4456Q qup-corequp-configqup-memory RRtxrx"cd,default  disabledi2c@a980002qcom,geni-i2c@ &n3seHn4456Q qup-corequp-configqup-memory RRtxrx"e,default  disabledspi@a980002qcom,geni-spi@ &n3seHn4456Q qup-corequp-configqup-memory RRtxrx"fg,default  disabledi2c@a9c0002qcom,geni-i2c@ 'n3seHn4456Q qup-corequp-configqup-memory RRtxrx"h,default  disabledspi@a9c0002qcom,geni-spi@ 'n3seHn4456Q qup-corequp-configqup-memory RRtxrx"ij,default  disableddma-controller@b00000*2qcom,x1e80100-gpi-dmaqcom,sm6350-gpi-dmaLMNOPQRSTUVW > 2V disabledfkgeniqup@bc00002qcom,geni-se-qup n33 m-ahbs-ahb 2C okayi2c@b800002qcom,geni-i2c@ un3seHn4456 qup-corequp-configqup-memory kktxrx"l,default  disabledspi@b800002qcom,geni-spi@ un3seHn4456 qup-corequp-configqup-memory kktxrx"mn,default  disabledi2c@b840002qcom,geni-i2c@@ Gn3seHn4456 qup-corequp-configqup-memory kktxrx"o,default  disabledspi@b840002qcom,geni-spi@@ Gn3seHn4456 qup-corequp-configqup-memory kktxrx"pq,default  disabledi2c@b880002qcom,geni-i2c@ Hn3seHn4456 qup-corequp-configqup-memory kktxrx"r,default  disabledspi@b880002qcom,geni-spi@ Hn3seHn4456 qup-corequp-configqup-memory kktxrx"st,default  disabledi2c@b8c0002qcom,geni-i2c@ In3seHn4456 qup-corequp-configqup-memory kktxrx"u,default  disabledspi@b8c0002qcom,geni-spi@ In3seHn4456 qup-corequp-configqup-memory kktxrx"vw,default  disabledi2c@b900002qcom,geni-i2c@ Jn3seHn4456 qup-corequp-configqup-memory kktxrx"x,default  disabledspi@b900002qcom,geni-spi@ Jn3seHn4456 qup-corequp-configqup-memory kktxrx"yz,default  disabledi2c@b940002qcom,geni-i2c@@ Kn3seHn4456 qup-corequp-configqup-memory kktxrx"{,default  disabledspi@b940002qcom,geni-spi@@ Kn3seHn4456 qup-corequp-configqup-memory kktxrx"|},default  disabledi2c@b980002qcom,geni-i2c@ n3seHn4456 qup-corequp-configqup-memory kktxrx"~,default  disabledspi@b980002qcom,geni-spi@ n3seHn4456 qup-corequp-configqup-memory kktxrx",default  disabledi2c@b9c0002qcom,geni-i2c@ n3seHn4456 qup-corequp-configqup-memory kktxrx",default  disabledspi@b9c0002qcom,geni-spi@ n3seHn4456 qup-corequp-configqup-memory kktxrx",default  disabledthermal-sensor@c271000"2qcom,x1e80100-tsensqcom,tsens-v2 ' " :uplowcriticalJXfthermal-sensor@c272000"2qcom,x1e80100-tsensqcom,tsens-v2 '  "0:uplowcriticalJXfthermal-sensor@c273000"2qcom,x1e80100-tsensqcom,tsens-v2 '0 "@:uplowcriticalJXfthermal-sensor@c274000"2qcom,x1e80100-tsensqcom,tsens-v2 '@ "P:uplowcriticalJXfphy@fd300082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phy0Tnnrefy36okayfphy@fd50002qcom,x1e80100-qmp-usb3-dp-phyP@ n333auxrefcom_auxusb3_pipe3y3D3O phycommonYnokayf.ports port@0endpointfport@1endpointfport@2endpointfphy@fd900082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTnnrefy37okayfphy@fda0002qcom,x1e80100-qmp-usb3-dp-phy@ n3 3"3#auxrefcom_auxusb3_pipe3y3E3P phycommonYnokayf/ports port@0endpointfport@1endpointfport@2endpointfphy@fde00082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTnnrefy38okayfphy@fdf0002qcom,x1e80100-qmp-usb3-dp-phy@ n3$3&3'auxrefcom_auxusb3_pipe3y3F3Q phycommonYnokayf0ports port@0endpointfport@1endpointfport@2endpointfinterconnect@15000002qcom,x1e80100-cnoc-mainPD!|finterconnect@16000002qcom,x1e80100-cnoc-cfg`f!|f6interconnect@16800002qcom,x1e80100-system-noch!|interconnect@16c00002qcom,x1e80100-pcie-south-anoclЀ!|finterconnect@16d00002qcom,x1e80100-pcie-center-anocmp!|interconnect@16e00002qcom,x1e80100-aggre1-nocnD!|fQinterconnect@17000002qcom,x1e80100-aggre2-nocp!|finterconnect@17400002qcom,x1e80100-pcie-north-anoct!|interconnect@17500002qcom,x1e80100-usb-center-anocu!|interconnect@17600002qcom,x1e80100-usb-north-anocvp!|finterconnect@17700002qcom,x1e80100-usb-south-anocw!|finterconnect@17800002qcom,x1e80100-mmss-nocx!|fpci@1bf8000pci2qcom,pcie-x1e80100`0p p@ppparfdbielbiatuconfigmhi 8p p0p0 `EFGHIJ(:msi0msi1msi2msi3msi4msi5msi6msi7)KLM8n3v3x3y3333"<auxcfgbus_masterbus_slaveslave_q2anoc_aggrcnoc_sf_axi73vG$0n 5pcie-memcpu-pciey3"3#pcilink_down3 \-jpciephyokay t ,default"phy@1bfc000"2qcom,x1e80100-qmp-gen4x2-pcie-phy (n3z3x3{3}auxcfg_ahbrefrchngpipey3%3$phyphy_nocsr73{G3 Ypcie6a_pipe_clknokayf-pci@1c08000pci2qcom,pcie-x1e80100`0||@||parfdbielbiatuconfigmhi 8| |0|0 `(:msi0msi1msi2msi3msi4msi5msi6msi7)8n3`3b3c3i3j33!<auxcfgbus_masterbus_slaveslave_q2anoc_aggrcnoc_sf_axi73`G$0n 5 pcie-memcpu-pciey33pcilink_down3\,jpciephyokay t ",defaultpcie@0pci phy@1c0e000"2qcom,x1e80100-qmp-gen3x2-pcie-phy (n3`3b3d3fauxcfg_ahbrefrchngpipey3phy73dG3Ypcie4_pipe_clknokayf,hwlock@1f400002qcom,tcsr-mutexf(clock-controller@1fc00002qcom,x1e80100-tcsrsysconnYfgpu@3d00000!2qcom,adreno-43050c01qcom,adreno0#kgsl_3d0_reg_memorycx_memcx_dbgc ,n5 gfx-memokayzap-shaderqcom/x1e80100/gen70500_zap.mbnopp-table2operating-points-v2fopp-1100000000A  opp-1000000000; ۳opp-9250000007"a@ @۳opp-800000000/ opp-744000000,X  opp-687000000( |copp-550000000 U \kopp-390000000> @-opp-300000000 8 gmu@3d6a000'2qcom,adreno-gmu-x185.1qcom,adreno-gmu0֠P (gmursccgmu_pdc01:hfigmu8n3$37!ahbgmucxoaximemnochubdemetcxgx $fopp-table2operating-points-v2fopp-550000000 U opp-220000000  @clock-controller@3d900002qcom,x1e80100-gpuccn*3536Yfiommu@3da0000B2qcom,x1e80100-smmu-500qcom,adreno-smmuqcom,smmu-500arm,mmu-500-:8>?@A n3738hlosbusifaceahbfinterconnect@264000002qcom,x1e80100-gem-noc&@1!|f5interconnect@320c00002qcom,x1e80100-nsp-noc2 !|fcodec@6aa0000:2qcom,x1e80100-lpass-wsa-macroqcom,sm8550-lpass-wsa-macro(nDfgmclkmacrodcodecfsgenY wsa2-mclkM^WSA2fsoundwire@6ab00002qcom,soundwire-v2.0.0niface pWSA2",defaultv ??         % B M disabledcodec@6ac000082qcom,x1e80100-lpass-rx-macroqcom,sm8550-lpass-rx-macro(n@fgmclkmacrodcodecfsgenYmclkMfsoundwire@6ad00002qcom,soundwire-v2.0.0niface pRX",defaultv           % B Mokayfcodec@0,42sdw20217010d00Zf codec@6ae000082qcom,x1e80100-lpass-tx-macroqcom,sm8550-lpass-tx-macro(n9fgmclkmacrodcodecfsgenYmclkMfcodec@6b00000:2qcom,x1e80100-lpass-wsa-macroqcom,sm8550-lpass-wsa-macro(nBfgmclkmacrodcodecfsgenYmclkM^WSAfsoundwire@6b100002qcom,soundwire-v2.0.0niface pWSA",defaultv ??         % B Mokayfspeaker@0,02sdw20217020400M o  ^SpkrLeft{fspeaker@0,12sdw20217020400M o  ^SpkrRight{fsoundwire@6d300002qcom,soundwire-v2.0.0niface :corewakeuppTX",defaultv %B Mokayfcodec@0,32sdw20217010d00f codec@6d4400082qcom,x1e80100-lpass-va-macroqcom,sm8550-lpass-va-macro@$n9fgmclkmacrodcodecYfsgenMfpinctrl@6e80000>2qcom,x1e80100-lpass-lpi-pinctrlqcom,sm8550-lpass-lpi-pinctrl %nfg coreaudioftx-swr-active-statefclk-pinsgpio0 swr_tx_clk data-pins gpio1gpio2 swr_tx_data "rx-swr-active-statefclk-pinsgpio3 swr_rx_clk data-pins gpio4gpio5 swr_rx_data "dmic01-default-stateclk-pinsgpio6 dmic1_clk0data-pinsgpio7 dmic1_data<dmic23-default-stateclk-pinsgpio8 dmic2_clk0data-pinsgpio9 dmic2_data<wsa-swr-active-statefclk-pinsgpio10 wsa_swr_clk data-pinsgpio11 wsa_swr_data "wsa2-swr-active-statefclk-pinsgpio15 wsa2_swr_clk data-pinsgpio16wsa2_swr_data "spkr-01-sd-n-active-stategpio12gpioIfinterconnect@7e400002qcom,x1e80100-lpass-ag-noc!|interconnect@74000002qcom,x1e80100-lpass-lpiaon-noc@!|interconnect@74300002qcom,x1e80100-lpass-lpicx-nocC!|fphy@88e000082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTnn refy39 disabledfusb@a0f88002qcom,x1e80100-dwc3qcom,dwc3 Hn333333 333Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys733G$ 4r:9 1:pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq3\y3A0n 56%usb-ddrapps-usbT okayusb@a000000 2snps,dwc3  a 2 0jusb2-phyusb3-phyb{hostports port@0endpointfport@1endpointfusb@a2f88002qcom,x1e80100-dwc3qcom,dwc3 / Hn333333 333Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys733G$ (21&:pwr_eventdp_hs_phy_irqdm_hs_phy_irq3\y3=0n 56"usb-ddrapps-usbT disabledusb@a200000 2snps,dwc3   2 jusb2-phy high-speedports port@0endpointusb@a6f88002qcom,x1e80100-dwc3qcom,dwc3 oHn3333 33 333Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys733G$ 4s=1:pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq3\y3?T okayusb@a600000 2snps,dwc3 ` c 2  .jusb2-phyusb3-phyb{hostports port@0endpointfport@1endpointfusb@a8f88002qcom,x1e80100-dwc3qcom,dwc3 Hn33 333 3 333Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys73 3 G$ 4t< /1:pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq3\y3@0n 56$usb-ddrapps-usbT okayusb@a800000 2snps,dwc3  e 2` /jusb2-phyusb3-phyb{hostports port@0endpointfport@1endpointfdisplay-subsystem@ae000002qcom,x1e80100-mdss mdss Sn3&:yHn5   56mdp0-memmdp1-memcpu-cfg 2s okayfdisplay-controller@ae010002qcom,x1e80100-dpu   mdpvbif(n3&=:Fnrt_busifacelutcorevsync1ports port@0endpointfport@4endpointfport@5endpointfport@6endpointfopp-table2operating-points-v2fopp-200000000 \opp-325000000_@\opp-375000000Z \opp-514000000\opp-575000000"E\displayport-controller@ae900002qcom,x1e80100-dpP      (n ;core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixel7..1.jdpM disabledports port@0endpointfport@1endpointfopp-table2operating-points-v2fopp-160000000 h\opp-270000000߀\opp-540000000 /\opp-8100000000G\displayport-controller@ae980002qcom,x1e80100-dpP      (n;core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixel7//1/jdpM disabledports port@0endpointfport@1endpointfopp-table2operating-points-v2fopp-160000000 h\opp-270000000߀\opp-540000000 /\opp-8100000000G\displayport-controller@ae9a0002qcom,x1e80100-dpP     (n"$'(;core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixel7%)0010jdpM disabledports port@0endpointfport@1endpointfopp-table2operating-points-v2fopp-160000000 h\opp-270000000߀\opp-540000000 /\opp-8100000000G\displayport-controller@aea00002qcom,x1e80100-dpP     (n-/23;core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixel7041jdpokayports port@0endpointfport@1endpoint `=Av1fopp-table2operating-points-v2fopp-160000000 h\opp-270000000߀\opp-540000000 /\opp-8100000000G\aux-buspanel 2edp-panelportendpointfphy@aec2a002qcom,x1e80100-dp-phy@ * " & n" auxcfg_ahb1Yn disabledphy@aec5a002qcom,x1e80100-dp-phy@ Z R V Pn- auxcfg_ahb1Ynokayfclock-controller@af000002qcom,x1e80100-dispcc dn*3%+..//001\Yfinterrupt-controller@b2200002qcom,x1e80100-pdcqcom,pdc "@dH**/ 4ca  0sfpower-management@c300000%2qcom,x1e80100-aoss-qmpqcom,aoss-qmp 0)) )Yfarbiter@c4000002qcom,x1e80100-spmi-pmic-arb0 @0 P@ Dcorechnlsobsrvr spmi@c42d000 B@ L cnfgintr :periph_irq s pmic@02qcom,pm8550qcom,spmi-pmic pon@13002qcom,pmk8350-pon hlospbspwrkey2qcom,pmk8350-pwrkey$tresin2qcom,pmk8350-resin disabledrtc@61002qcom,pmk8350-rtcab rtcalarmb reservednvram@71002qcom,spmi-sdamq  qreboot-reason@48H/gpio@8800!2qcom,pmk8550-gpioqcom,spmi-gpiosfpmic@12qcom,pm8550qcom,spmi-pmic temp-alarm@a002qcom,spmi-temp-alarm  Xfgpio@8800 2qcom,pm8550-gpioqcom,spmi-gpio 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qup1_se3{f\qup-i2c12-data-clk-stategpio48gpio49 qup1_se4{f_qup-i2c13-data-clk-stategpio52gpio53 qup1_se5{fbqup-i2c14-data-clk-stategpio56gpio57 qup1_se6{fequp-i2c15-data-clk-stategpio54gpio55 qup1_se7{fhqup-i2c16-data-clk-stategpio64gpio65 qup2_se0{f8qup-i2c17-data-clk-stategpio68gpio69 qup2_se1{f;qup-i2c18-data-clk-stategpio72gpio73 qup2_se2{f>qup-i2c19-data-clk-stategpio76gpio77 qup2_se3{fAqup-i2c20-data-clk-stategpio80gpio81 qup2_se4{fDqup-i2c21-data-clk-stategpio84gpio85 qup2_se5{fGqup-i2c22-data-clk-stategpio88gpio89 qup2_se6{fKqup-i2c23-data-clk-stategpio86gpio87 qup2_se7{fNqup-spi0-cs-stategpio3 qup0_se0fnqup-spi0-data-clk-stategpio0gpio1gpio2 qup0_se0fmqup-spi1-cs-stategpio7 qup0_se1fqqup-spi1-data-clk-stategpio4gpio5gpio6 qup0_se1fpqup-spi2-cs-stategpio11 qup0_se2ftqup-spi2-data-clk-stategpio8gpio9gpio10 qup0_se2fsqup-spi3-cs-stategpio15 qup0_se3fwqup-spi3-data-clk-stategpio12gpio13gpio14 qup0_se3fvqup-spi4-cs-stategpio19 qup0_se4fzqup-spi4-data-clk-stategpio16gpio17gpio18 qup0_se4fyqup-spi5-cs-stategpio23 qup0_se5f}qup-spi5-data-clk-stategpio20gpio21gpio22 qup0_se5f|qup-spi6-cs-stategpio27 qup0_se6fqup-spi6-data-clk-stategpio24gpio25gpio26 qup0_se6fqup-spi7-cs-stategpio13 qup0_se7fqup-spi7-data-clk-stategpio14gpio15gpio12 qup0_se7fqup-spi8-cs-stategpio35 qup1_se0fUqup-spi8-data-clk-stategpio32gpio33gpio34 qup1_se0fTqup-spi9-cs-stategpio39 qup1_se1fXqup-spi9-data-clk-stategpio36gpio37gpio38 qup1_se1fWqup-spi10-cs-stategpio43 qup1_se2f[qup-spi10-data-clk-stategpio40gpio41gpio42 qup1_se2fZqup-spi11-cs-stategpio47 qup1_se3f^qup-spi11-data-clk-stategpio44gpio45gpio46 qup1_se3f]qup-spi12-cs-stategpio51 qup1_se4faqup-spi12-data-clk-stategpio48gpio49gpio50 qup1_se4f`qup-spi13-cs-stategpio55 qup1_se5fdqup-spi13-data-clk-stategpio52gpio53gpio54 qup1_se5fcqup-spi14-cs-stategpio59 qup1_se6fgqup-spi14-data-clk-stategpio56gpio57gpio58 qup1_se6ffqup-spi15-cs-stategpio53 qup1_se7fjqup-spi15-data-clk-stategpio54gpio55gpio52 qup1_se7fiqup-spi16-cs-stategpio67 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interrupt-parent#address-cells#size-cellsmodelcompatiblestdout-pathclock-frequency#clock-cellsphandleclocksclock-multclock-divdevice_typeregenable-methodnext-level-cachepower-domainspower-domain-namescpu-idle-statescache-levelcache-unifiedcpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usinterconnects#interconnect-cellsqcom,bcm-votersinterrupts#power-domain-cellsdomain-idle-statesrangesno-maphwlockssizereusablelinux,cma-defaultinterrupts-extendedmboxesqcom,smemqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#reset-cells#mbox-cellsdma-channelsdma-channel-mask#dma-cellsiommusstatusclock-namesinterconnect-namesdmasdma-namespinctrl-0pinctrl-namesinterrupt-names#qcom,sensors#thermal-sensor-cells#phy-cellsresetsvdd-supplyvdda12-supplyphysreset-namesvdda-phy-supplyvdda-pll-supplyremote-endpointreg-namesbus-rangedma-coherentlinux,pci-domainnum-lanesinterrupt-map-maskinterrupt-mapassigned-clocksassigned-clock-ratesrequired-oppsphy-namesperst-gpioswake-gpiosvddpe-3v3-supplyclock-output-names#hwlock-cellsoperating-points-v2qcom,gmu#cooling-cellsmemory-regionfirmware-nameopp-hzopp-levelopp-peak-kBpsqcom,qmp#iommu-cells#global-interrupts#sound-dai-cellssound-name-prefixlabelqcom,din-portsqcom,dout-portsqcom,ports-sintervalqcom,ports-offset1qcom,ports-offset2qcom,ports-hstartqcom,ports-hstopqcom,ports-word-lengthqcom,ports-block-pack-modeqcom,ports-block-group-countqcom,ports-lane-controlqcom,rx-port-mappingreset-gpiosvdd-1p8-supplyvdd-io-supplyqcom,ports-sinterval-lowqcom,tx-port-mappinggpio-controller#gpio-cellsgpio-rangespinsfunctiondrive-strengthslew-ratebias-disablebias-bus-holdoutput-highinput-enableoutput-lowwakeup-sourcesnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,usb3_lpm_capabledr_modemaximum-speedassigned-clock-parentsdata-laneslink-frequenciespower-supplyqcom,pdc-rangesqcom,eeqcom,channellinux,codebits#pwm-cellsvdd18-supplyvdd3-supplywakeup-parentgpio-reserved-rangesbias-pull-up#redistributor-regionsredistributor-stridemsi-controller#msi-cellsqcom,tcs-offsetqcom,drv-idqcom,tcs-configqcom,pmic-idvdd-bob1-supplyvdd-bob2-supplyvdd-l1-l4-l10-supplyvdd-l2-l13-l14-supplyvdd-l5-l16-supplyvdd-l6-l7-supplyvdd-l8-l9-supplyvdd-l12-supplyvdd-l15-supplyvdd-l17-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-modevdd-l1-supplyvdd-l2-supplyvdd-l3-supplyvdd-s4-supplyvdd-s1-supplyvdd-s2-supplyvdd-s5-supplyframe-numberqcom,smem-statesqcom,smem-state-namesqcom,glink-channelsqcom,non-secure-domainqcom,domainqcom,intentsqcom,protection-domainthermal-sensorstemperaturehysteresispolling-delay-passiveserial0qcom,micbias1-microvoltqcom,micbias2-microvoltqcom,micbias3-microvoltqcom,micbias4-microvoltqcom,mbhc-buttons-vthreshold-microvoltqcom,mbhc-headset-vthreshold-microvoltqcom,mbhc-headphone-vthreshold-microvoltqcom,rx-deviceqcom,tx-devicevdd-buck-supplyvdd-rxtx-supplyvdd-mic-bias-supplyorientation-gpiospower-roledata-roleaudio-routinglink-namesound-dairegulator-always-onregulator-boot-ongpioenable-active-high