8( ά ,radxa,rock-3crockchip,rk35667Radxa ROCK 3Caliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000/mmc@fe2c0000cpus cpu@0cpu,arm,cortex-a55 psci*>K@]jw@ cpu@100cpu,arm,cortex-a55 psci*>K@]jw@ cpu@200cpu,arm,cortex-a55 psci*>K@]jw@ cpu@300cpu,arm,cortex-a55 psci*>K@]jw@ l3-cache,cache@M@_opp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc" protocol@14(opp-table-1,operating-points-v2Dopp-200000000   P PB@opp-300000000  P PB@opp-400000000ׄ  P PB@opp-600000000#F  B@opp-700000000)' ~~B@opp-800000000/ B@B@B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codecsimple-audio-card,cpu pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0#smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24m(xin32k ,fixed-clockxin32kdefault(sram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBhost Jutmi_wide4SZokay usb2-phys zhigh-speedusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4SZokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  A(usb@fd800000 ,generic-ehci usbokayusb@fd840000 ,generic-ohci usbokayusb@fd880000 ,generic-ehci usbokayusb@fd8c0000 ,generic-ohci usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd_io-domains&,rockchip,rk3568-pmu-io-voltage-domainokay &4Bsyscon@fdc50000 ,rockchip,rk3566-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru(Pclock-controller@fdd20000,rockchip,rk3568-cruxin24m(P] mG  i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk!default okayregulator@1c ,tcs,tcs4525vdd_cpu 50(="regulator-state-memHpmic@20,rockchip,rk809 #rk808-clkout1rk808-clkout2default$%ay&&&&&&&&&(regulatorsDCDC_REG1 vdd_logic p(qregulator-state-memH DCDC_REG2vdd_gpu p(qEregulator-state-memH DCDC_REG3vcc_ddrregulator-state-mem&DCDC_REG4vdd_npu p(qregulator-state-memHDCDC_REG5vcc_1v8w@w@regulator-state-memHLDO_REG1vdda0v9_image  [regulator-state-memHLDO_REG2 vdda_0v9  regulator-state-memHLDO_REG3 vdda0v9_pmu  regulator-state-mem& LDO_REG4 vccio_acodec2Z2Zregulator-state-memHLDO_REG5 vccio_sdw@2Zregulator-state-memHLDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem& 2ZLDO_REG7 vcca_1v8w@w@regulator-state-memHLDO_REG8 vcca1v8_pmuw@w@regulator-state-mem& w@LDO_REG9vcca1v8_imagew@w@\regulator-state-memHSWITCH_REG1vcc_3v3regulator-state-memHSWITCH_REG2 vcc3v3_sdregulator-state-memHeeprom@50,belling,bl24c16aatmel,24c16P>serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclkG''(defaultLY disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)defaultc disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk*defaultc disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk+defaultc disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk,defaultc disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllern power-domain@7-npower-domain@8 ./0npower-domain@9  123npower-domain@10 456789npower-domain@11 :npower-domain@13 ;npower-domain@14 <=>npower-domain@15?@ABCngpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpugpubus *D4okayEvideo-codec@fdea0400,rockchip,rk3568-vpu vdpu aclkhclkF4 iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface4 Frga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkS&$% coreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkG4 iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface4 Gmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрSreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refS stmmaceth HIJ%okay] K.input;L Frgmii-idOdefaultMNOPQRmdio,snps,dwmac-mdio ethernet-phy@1,ethernet-phy-ieee802.3-c22ZN j |SLstmmac-axi-configHrx-queues-configIqueue0tx-queues-configJqueue0vop@fe040000 0@vopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2T4  okay,rockchip,rk3566-vop]ports port@0 endpoint@2U]port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface4 okayTdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi DpclkdphyV4 apbS  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi EpclkdphyW4 apbS  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault XYZ4 L okay [\ports port@0endpoint]Uport@1endpoint^qos@fe128000,rockchip,rk3568-qossyscon -qos@fe138080,rockchip,rk3568-qossyscon <qos@fe138100,rockchip,rk3568-qossyscon =qos@fe138180,rockchip,rk3568-qossyscon >qos@fe148000,rockchip,rk3568-qossyscon .qos@fe148080,rockchip,rk3568-qossyscon /qos@fe148100,rockchip,rk3568-qossyscon 0qos@fe150000,rockchip,rk3568-qossyscon :qos@fe158000,rockchip,rk3568-qossyscon 4qos@fe158100,rockchip,rk3568-qossyscon 5qos@fe158180,rockchip,rk3568-qossyscon 6qos@fe158200,rockchip,rk3568-qossyscon 7qos@fe158280,rockchip,rk3568-qossyscon 8qos@fe158300,rockchip,rk3568-qossyscon 9qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon ?qos@fe190280,rockchip,rk3568-qossyscon @qos@fe190300,rockchip,rk3568-qossyscon Aqos@fe190380,rockchip,rk3568-qossyscon Bqos@fe190400,rockchip,rk3568-qossyscon Cqos@fe198000,rockchip,rk3568-qossyscon ;qos@fe1a8000,rockchip,rk3568-qossyscon 1qos@fe1a8080,rockchip,rk3568-qossyscon 2qos@fe1a8100,rockchip,rk3568-qossyscon 3dfi@fe230000,rockchip,rk3568-dfi#  )_pcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGsyspmcmsglegacyerr6($aclk_mstaclk_slvaclk_dbipclkauxpci@`S````ar pcie-phy4T @@Spipe okaydefaulta |b clegacy-interrupt-controller H`mmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрSresetokaydefaultdefg& mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрSresetokay   0h ;default ijk I& spi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfcldefaultokay flash@0,jedec,spi-nor W2 i zmmc@fe310000,rockchip,rk3568-dwcmshc1 ]{}m n6(|zy{}corebusaxiblocktimerokay   ;defaultmnop i2s@fe400000,rockchip,rk3568-i2s-tdm@ 4]=AmFqFq?C9mclk_txmclk_rxhclkGq txSPQ tx-mrx-m okay i2s@fe410000,rockchip,rk3568-i2s-tdmA 5]EImFqFqGK:mclk_txmclk_rxhclkGqq rxtxSRS tx-mrx-m defaultrstuokay i2s@fe420000,rockchip,rk3568-i2s-tdmB 6]MmFqOO;mclk_txmclk_rxhclkGqq txrxSTtx-m defaultvwxy disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclkGqq txrxSUV tx-mrx-m  disabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclkGq  rxz{|}~defaultSXpdm-m disabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\Gq txdefault disableddma-controller@fe530000,arm,pl330arm,primecellS@    apb_pclk 'dma-controller@fe550000,arm,pl330arm,primecellU@   apb_pclk qi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclkdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclkdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclkdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclkdefault  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclkG'' txrxdefault   disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclkG'' txrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclkG'' txrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclkG'' txrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclkG'' defaultLYokayserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclkG''defaultLYokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclkG''defaultLY disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclkG'' defaultLY disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclkG' ' defaultLY disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclkG' ' defaultLY disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclkG''defaultLY disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclkG''defaultLY disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclkG''defaultLY disabledthermal-zonescpu-thermal d  tripscpu_alert0 p !passivecpu_alert1 $ !passivecpu_crit s ! criticalcooling-mapsmap0 ,0 1 gpu-thermal   tripsgpu-threshold p !passivegpu-target $ !passivegpu-crit s ! criticalcooling-mapsmap0 , 1tsadc@fe710000,rockchip,rk3568-tsadcq s]mf@ `tsadcapb_pclkS  @sdefaultsleep W aokay w saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkS saradc-apb okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultc disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultc disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultc disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultc disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultc disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultc disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultc disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultc disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultc disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultc disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultc disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultc disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe]"mS   okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe]%mS   okayphy@fe870000,rockchip,rk3568-csi-dphyypclk Sapb  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz 4 apbS disabledVmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ 4 apbS disabledWusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m  (okayhost-port okayOotg-port okayOusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m  (okayhost-port okayOotg-port okayOpinctrl,rockchip,rk3568-pinctrl )_ gpio@fdd60000,rockchip,gpio-bank !.     &#gpio@fe740000,rockchip,gpio-bankt "cd    &bgpio@fe750000,rockchip,gpio-banku #ef  @  &gpio@fe760000,rockchip,gpio-bankv $gh  `  &Sgpio@fe770000,rockchip,gpio-bankw %ij    &pcfg-pull-up 2pcfg-pull-none ?pcfg-pull-none-drv-level-1 ? Lpcfg-pull-none-drv-level-2 ? Lpcfg-pull-none-drv-level-3 ? Lpcfg-pull-up-drv-level-1 2 Lpcfg-pull-up-drv-level-2 2 Lpcfg-pull-none-smt ? [acodecaudiopwmbt656bt1120camvcc_cam_en pcan0can1can2cifclk32kclk32k-out0 pcpuebcedpdpemmcemmc-bus8 p  memmc-clk pnemmc-cmd poemmc-datastrobe ppeth0eth1flashfspifspi-pins` plgmac0gmac1gmac1m1-miim pMgmac1m1-clkinout pRgmac1m1-rx-bus20 p Ogmac1m1-tx-bus20 pNgmac1m1-rgmii-clk pPgmac1m1-rgmii-bus@ pQgpuhdmitxhdmitxm0-cec pZhdmitx-scl pXhdmitx-sda pYi2c0i2c0-xfer p  !i2c1i2c1-xfer p  i2c2i2c2m0-xfer p i2c3i2c3m0-xfer pi2c4i2c4m0-xfer p  i2c5i2c5m0-xfer p  i2s1i2s1m0-lrcktx psi2s1m0-mclk p%i2s1m0-sclktx pri2s1m0-sdi0 p ti2s1m0-sdo0 pui2s2i2s2m0-lrcktx pwi2s2m0-sclktx pvi2s2m0-sdi pxi2s2m0-sdo pyi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk pzpdmm0-clk1 p{pdmm0-sdi0 p |pdmm0-sdi1 p }pdmm0-sdi2 p ~pdmm0-sdi3 ppmicpmic-int-l p$pmupwm0pwm0m0-pins p)pwm1pwm1m0-pins p*pwm2pwm2m0-pins p+pwm3pwm3-pins p,pwm4pwm4-pins ppwm5pwm5-pins ppwm6pwm6-pins ppwm7pwm7-pins ppwm8pwm8m0-pins p pwm9pwm9m0-pins p pwm10pwm10m0-pins p pwm11pwm11m0-pins ppwm12pwm12m0-pins ppwm13pwm13m0-pins ppwm14pwm14m0-pins ppwm15pwm15m0-pins prefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ pdsdmmc0-clk pesdmmc0-cmd pfsdmmc0-det pgsdmmc1sdmmc1-bus4@ pisdmmc1-clk pjsdmmc1-cmd pksdmmc2spdifspdifm0-tx pspi0spi0m0-pins0 p spi0m0-cs0 pspi0m0-cs1 pspi1spi1m0-pins0 p spi1m0-cs0 pspi1m0-cs1 pspi2spi2m0-pins0 pspi2m0-cs0 pspi2m0-cs1 pspi3spi3m0-pins0 p  spi3m0-cs0 pspi3m0-cs1 ptsadctsadc-shutorg ptsadc-pin puart0uart0-xfer p(uart1uart1m0-xfer p  uart1m0-ctsn puart1m0-rtsn p uart2uart2m0-xfer puart3uart3m0-xfer puart4uart4m0-xfer puart5uart5m0-xfer puart6uart6m0-xfer puart7uart7m0-xfer puart8uart8m0-xfer puart9uart9m0-xfer pvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2bluetoothbt-reg-on-h pbt-wake-host-h p bt-host-wake-h p displayvcc_mipi_en pledsuser-led2 ppciepcie-pwr-en ppcie-reset-h p ausbvcc5v0-usb30-host-en pvcc5v0-usb-otg-en pwifiwifi-host-wake-h pwifi-reg-on-h pchosen ~serial2:1500000n8external-gmac1-clock ,fixed-clocksY@ gmac1_clkin(Khdmi-con,hdmi-connectoraportendpoint^leds ,gpio-ledsled-0 # heartbeat  heartbeatdefaultsdio-pwrseq,mmc-pwrseq-simple ext_clockdefault d LK@ |#hvcc5v-dcin-regulator,regulator-fixed vcc5v_dcinLK@LK@vcc3v3-pcie-regulator,regulator-fixed  #default vcc3v3_pcie2Z2Z=&cvcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z="&vcc5v0-sys-regulator,regulator-fixed vcc5v0_sysLK@LK@="vcc5v0-usb30-host-regulator,regulator-fixed  #defaultvcc5v0_usb30_hostLK@LK@="vcc5v0-usb-otg-regulator,regulator-fixed  #defaultvcc5v0_usb_otgLK@LK@="vcc-cam-regulator,regulator-fixed  #defaultvcc_cam2Z2Z=&regulator-state-memHvcc-mipi-regulator,regulator-fixed  #default vcc_mipi2Z2Z=&regulator-state-memH interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconmaximum-speedinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-suspend-microvoltregulator-on-in-suspendpagesizedmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpoint#sound-dai-cellsavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr50vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104spi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthmmc-hs200-1_8vdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-pathfunctioncolorlinux,default-triggerpost-power-on-delay-mspower-off-delay-usenable-active-highgpio