C88( 8 ,Freescale i.MX8QM MEK2fsl,imx8qm-mekfsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000l/bus@5a000000/spi@5a000000q/bus@5a000000/spi@5a010000v/bus@5a000000/spi@5a020000{/bus@5a000000/spi@5a030000 /vpu@2c000000/vpu-core@2d080000 /vpu@2c000000/vpu-core@2d090000 /vpu@2c000000/vpu-core@2d0a0000cpus cpu@0cpu2arm,cortex-a53 psci@@,@O cpu@1cpu2arm,cortex-a53 psci@@,@O cpu@2cpu2arm,cortex-a53 psci@@,@O cpu@3cpu2arm,cortex-a53 psci@@,@O l2-cache02cacheWc@Ol2-cache12cacheWc@opp-table-02operating-points-v2qOopp-600000000|#F Iopp-896000000|5gB@Iopp-1104000000|AʹIopp-1200000000|GIopp-table-12operating-points-v2qopp-600000000|#FB@Iopp-1056000000|>HB@Iopp-1296000000|M?dIopp-1596000000|_!Iinterrupt-controller@51a00000 2arm,gic-v3PQQ R RR  Opmu2arm,armv8-pmuv3 psci 2arm,psci-1.0smctimer2arm,armv8-timer0   iommu@51400000 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9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkOclock-controller@5b2300002fsl,imx8qxp-lpcg[#%0 enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkOclock-controller@5b2400002fsl,imx8qxp-lpcg[$%0 enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkOclock-controller@5b2700002fsl,imx8qxp-lpcg['%"usboh3_ahb_clkusboh3_phy_ipg_clkOclock-controller@5b2800002fsl,imx8qxp-lpcg[(%0Musb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclkOclock-controller@5b2900002fsl,imx8qxp-lpcg[)%   'gpmi_bchgpmi_iogpmi_apbgpmi_bch_apb Oclock-controller@5b2900042fsl,imx8qxp-lpcg[)% apbhdma_hclk Odma-controller@5b810000(2fsl,imx8qxp-dma-apbhfsl,imx28-dma-apbh[ 0#. Onand-controller@5b8120002fsl,imx8qxp-gpmi-nand[ [@  gpmi-nandbch  bch 'gpmi_iogpmi_apbgpmi_bchgpmi_bch_apbrx-tx  9 I $disabledclock-lsio-bus 2fixed-clock% lsio_bus_clkObus@5d000000 2simple-bus  ]]pwm@5d0000002fsl,imx27-pwm]ipgper 9In6 ^ $disabledpwm@5d0100002fsl,imx27-pwm]ipgper 9In6 _ $disabledpwm@5d0200002fsl,imx27-pwm]ipgper 9In6 ` $disabledpwm@5d0300002fsl,imx27-pwm]ipgper 9In6 a $disabledgpio@5d080000] ^n2fsl,imx8qm-gpiofsl,imx35-gpio0n$Ogpio@5d090000]  ^n2fsl,imx8qm-gpiofsl,imx35-gpio@n(2 ?HOgpio@5d0a0000]  ^n2fsl,imx8qm-gpiofsl,imx35-gpio0nPUh gpio@5d0b0000]  ^n2fsl,imx8qm-gpiofsl,imx35-gpionruOzgpio@5d0c0000]  ^n2fsl,imx8qm-gpiofsl,imx35-gpio`n Ogpio@5d0d0000]  ^n2fsl,imx8qm-gpiofsl,imx35-gpion Ogpio@5d0e0000] ^n2fsl,imx8qm-gpiofsl,imx35-gpio n  gpio@5d0f0000] ^n2fsl,imx8qm-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi] fspi_basefspi_mmap \ fspi_enfspi$okay2default@flash@0 2jedec,spi-norzk@mailbox@5d1b0000] s $disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000] s,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-muOmailbox@5d1d0000] s $disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000] s $disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000] s $disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000]  s$okay2fsl,imx8qm-mufsl,imx6sx-muOmailbox@5d210000]! s$okay2fsl,imx8qm-mufsl,imx6sx-muOmailbox@5d280000]( s2fsl,imx8qm-mufsl,imx6sx-muOclock-controller@5d4000002fsl,imx8qxp-lpcg]@%4hpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkOclock-controller@5d4100002fsl,imx8qxp-lpcg]A%4hpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkOclock-controller@5d4200002fsl,imx8qxp-lpcg]B%4hpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkOclock-controller@5d4300002fsl,imx8qxp-lpcg]C%4hpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkOclock-controller@5d4400002fsl,imx8qxp-lpcg]D%4hpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkclock-controller@5d4500002fsl,imx8qxp-lpcg]E%4hpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkclock-controller@5d4600002fsl,imx8qxp-lpcg]F%4hpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkclock-controller@5d4700002fsl,imx8qxp-lpcg]G%4hpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkclock-hsio-axi 2fixed-clock%ׄ hsio_axi_clkOclock-hsio-per 2fixed-clock%U hsio_per_clkOclock-hsio-refa2gpio-gate-clock% Oclock-hsio-refb2gpio-gate-clock% clock-xtal100m 2fixed-clock% xtal_100MHzObus@5f000000 2simple-bus0__@`p pcie@5f0100002fsl,imx8q-pcie_  dbiconfig0fhmsidma  dbimstrslvpciijkl $disabled% *pcie-phy@2default pcie-ep@5f0100002fsl,imx8q-pcie-ep_ dbiaddr_space hdma dbimstrslv&5 $disabledclock-controller@5f0600002fsl,imx8qxp-lpcg_ % Fhsio_pcieb_mstr_axi_clkhsio_pcieb_slv_axi_clkhsio_pcieb_dbi_axi_clkOclock-controller@5f0b00002fsl,imx8qxp-lpcg_ %hsio_phyx1_per_clkOclock-controller@5f0d00002fsl,imx8qxp-lpcg_ %hsio_pcieb_per_clkOclock-controller@5f0f00002fsl,imx8qxp-lpcg_%hsio_misc_per_clkOpcie@5f0000002fsl,imx8q-pcie_O  dbiconfig0O@@ Fmsi  dbimstrslvpciIJKL$okay% *pcie-phy@2default Dpcie-ep@5f0000002fsl,imx8q-pcie-ep_@ dbiaddr_space Hdma dbimstrslv&5 $disabledsata@5f0200002fsl,imx8qm-ahci_ Xsatasata_ref*sata-phycali-phy0cali-phy10%$okayclock-controller@5f0500002fsl,imx8qxp-lpcg_ % Fhsio_pciea_mstr_axi_clkhsio_pciea_slv_axi_clkhsio_pciea_dbi_axi_clkOclock-controller@5f0700002fsl,imx8qxp-lpcg_%hsio_sata_clkOclock-controller@5f0800002fsl,imx8qxp-lpcg_%Lhsio_phyx2_pclk_0hsio_phyx2_pclk_1hsio_phyx2_apbclk_0hsio_phyx2_apbclk_1Oclock-controller@5f0900002fsl,imx8qxp-lpcg_ %Qhsio_phyx1_pclkhsio_phyx1_epcs_tx_clkhsio_phyx1_epcs_rx_clkhsio_phyx1_apb_clkOclock-controller@5f0a00002fsl,imx8qxp-lpcg_ %hsio_phyx2_per_clkOclock-controller@5f0c00002fsl,imx8qxp-lpcg_ %hsio_pciea_per_clkOclock-controller@5f0e00002fsl,imx8qxp-lpcg_%hsio_sata_per_clkOphy@5f1800002fsl,imx8qm-hsio ____ regphyctrlmiscpvpclk0pclk1apb_pclk0apb_pclk1pclk2epcs_txepcs_rxapb_pclk2phy0_crrphy1_crrctl0_crrctl1_crrctl2_crrmisc_crrc$okayQpciea-pcieb-sata^inputOchosenr/bus@5a000000/serial@5a060000memory@80000000memory@reserved-memory memory@90000000~Omemory@90008000~Omemory@90010000~Omemory@90018000~Omemory@900ff000~Omemory@90100000~Omemory@90108000~Omemory@90110000~Omemory@90118000~Omemory@901ff000~Omemory@904000002shared-dma-pool@~Omemory@92400000@~Omemory@942f0000/~Omemory@942f8000/~Omemory@943000002shared-dma-pool0~Obacklight-lvds02pwm-backlightddPbacklight-lvds12pwm-backlightddPmux-controller2nxp,cbdtu02043gpio-sbu-mux2default@  portendpointOusdhc2-vmmc2regulator-fixed SD1_SPWR- - ! +Oregulator-audio2regulator-fixedcs42888_supply2Z 2ZOregulator-fec2-nvcc2regulator-fixed fec2_nvccw@ w@ ! +Oregulator-can01-gen2regulator-fixed can01-en2Z 2Z ! +Oregulator-can2-gen2regulator-fixedcan2-en2Z 2Z ! +Oregulator-can01-stby2regulator-fixed can01-stby2Z 2Z ! + >Oregulator-can2-stby2regulator-fixed can2-stby2Z 2Z ! + >Oregulator-pcie2regulator-fixed@2default 2Z2Z mpcie_3v3 !  +Oregulator-adc-vref2regulator-fixed vref_1v8w@ w@Oregulator-audio-pwr2regulator-fixed audio-5vLK@ LK@ I ]Oregulator-audio-3v32regulator-fixed audio-3v32Z 2Z I ]Oregulator-audio-1v82regulator-fixed audio-1v8w@ w@ I ]Oaudio-codec-bt 2linux,bt-scoOsound-bt-sco2simple-audio-card obt-sco-audio dsp_a   simple-audio-card,cpu   Osimple-audio-card,codec sound-cs428882fsl,imx-audio-cs42888 ,imx-cs42888 3 = I TLine Out JackAOUT1LLine Out JackAOUT1RLine Out JackAOUT2LLine Out JackAOUT2RLine Out JackAOUT3LLine Out JackAOUT3RLine Out JackAOUT4LLine Out JackAOUT4RAIN1LLine In JackAIN1RLine In JackAIN2LLine In JackAIN2RLine In Jacksound-wm89602fsl,imx-audio-wm8960 ,wm8960-audio 3 = b THeadphone JackHP_LHeadphone JackHP_RExt SpkSPK_LPExt SpkSPK_LNExt SpkSPK_RPExt SpkSPK_RNLINPUT1Mic JackMic JackMICBimx8qm-cm4-02fsl,imx8qm-cm4  txrxrxdb$ +) n ~4imx8qm-cm4-12fsl,imx8qm-cm4  txrxrxdb$ +*= n* ~8 interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3spi0spi1spi2spi3vpu-core0vpu-core1vpu-core2device_typeregclocksenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterrupts#global-interrupts#iommu-cellsmbox-namesmboxes#power-domain-cells#clock-cellspinctrl-namespinctrl-0fsl,pinsread-only#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-frequencyclock-output-namesrangesclock-namespower-domainsfirmware-namestatusmemory-regionassigned-clocksassigned-clock-ratesgpio-controller#gpio-cellsVA-supplyVD-supplyVLS-supplyVLC-supplyreset-gpiosclock-indicesdmasdma-namesfsl,asrc-ratefsl,asrc-widthfsl,asrc-clk-mapassigned-clock-parents#sound-dai-cells#dma-cellsdma-channelsdma-channel-maskfsl,sai-asynchronousdaisfsl,dataline#mbox-cellsfsl,channelfsl,num-irqs#pwm-cellscs-gpioslabelpower-roledata-rolesource-pdosremote-endpointpinctrl-1scl-gpiossda-gpioswlf,shared-lrclkwlf,hp-cfgwlf,gpio-cfgAVDD-supplyDBVDD-supplyDCVDD-supplySPKVDD1-supplySPKVDD2-supply#io-channel-cellsvref-supplyfsl,clk-sourcefsl,scu-indexxceiver-supplyfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#index-cellsiommusbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetphy-supplynvmem-cellsnvmem-cell-namesrx-internal-delay-psreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-sizedr_modeusb-role-switch#phy-cellsgpio-rangesspi-max-frequencyspi-tx-bus-widthspi-rx-bus-widthenable-gpiosdma-rangesbus-rangeinterrupt-mapinterrupt-map-masknum-lanesnum-viewportfsl,max-link-speedreset-gpionum-ib-windowsnum-ob-windowsvpcie-supplyfsl,hsio-cfgfsl,refclk-pad-modestdout-pathno-mappwmsbrightness-levelsnum-interpolated-stepsdefault-brightness-levelselect-gpiosorientation-switchregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highvin-supplyregulator-always-onregulator-boot-onsimple-audio-card,namesimple-audio-card,formatsimple-audio-card,bitclock-inversionsimple-audio-card,frame-mastersimple-audio-card,bitclock-mastersound-daidai-tdm-slot-numdai-tdm-slot-widthaudio-cpuaudio-codecaudio-asrcaudio-routinghp-det-gpiofsl,resource-idfsl,entry-address